SU1734094A1 - Device for convolution to the optional modulus - Google Patents

Abstract

The invention relates to computing and can be used in the construction of diagnosable systems. The purpose of the invention is to reduce the hardware cost of the device. When a trigger signal is applied to the input 13 of the device, the controlled number is rewritten from the information input 21 of the device to the register 2 via the switch 1, and the monitoring module from the input 22 of the device to the register 3. Comparison units of group 4 compare the contents of register 2 (output 14) with the contents of register 3 (output 15) multiplied by 2, where 1 j k (k is the number of blocks in group 4). Subtract in blocks

Description

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In group 6, the spacing is calculated between the contents of register 2 and the contents of register 3 multiplied by 2J. The outputs 18 of the subtraction unit 6 are fed to the inputs of a multiplexer 7, which is controlled by the output 17 of the decoder 12, passing the minimum difference between the contents of registers 2 and 3 to the output 19 of multiplexer 7. This smallest difference through the switch 1 is written back to the register.

The invention relates to computing and can be used in the play of diagnosable systems.

The circuit of the invention is to reduce the hardware cost of the device.

FIG. 1 shows a functional diagram of the device; Fig, 2. 3 - examples of the implementation of a multiplexer) and a decoder.

The device (Fig. 1) contains a switch-1, registers 2 and 3, a group of comparison blocks 4, a comparison block 5, a group of subtraction blocks b, a multiplexer 7, a group of And 8 elements, a HE 9 element, an And 10 element, a clock pulse generator 11 decoder 12, device start input 13, outputs 14, 15 of the first and second registers 2 and 3, respectively, outputs 16 of the group comparison units 4, output 17 of the decoder 12, outputs 18 of the group B subtraction blocks, output (9 multiplexer 7, information device output 20, device information input 21, device control module input 22 Islands, an OR gate 23,

Multiplexer 1 (FIG. 2) contains switches 24.

The decoder 12 (Fig, 3) contains a group of elements And 25, the encoder 26, the inputs 27 of the encoder 26, the group 28 elements NOT.

The device works as follows.

3QM,

In the initial state, the registers 2, 3 are either zeroed (the reset chains are not shown), or contain data from the previous residual calculation (on register 2 is the binary code of the remainder, on the register is the 3-binary code of the module) In the first case, from the output of Less than 5 comparison block the zero signal is removed and the elements AND 8 of the group are closed, and a single signal from the output of the element NOT 9 allows the clock signal from the generator 11 to pass through the element 10 and the element OR 23 to the input of the register 2, which does not affect the operation of the device. In the second case, from the output of block 5, the comparison is removed from the single signal, the opening eletprocess continues until the contents of register 2 become less than the contents of the register. In this case, the signal from the output of the comparison unit 5 will allow the passage of the code from the output 14 of register 2 through the elements AND of group 8 to the information output 20 of the device. The organization of the computation cycle of the remainder is provided by the element NOT 9, the element AND 10, the generator of 11 clock pulses and the element OR 23.1 of the table., 3 Il.

Copies AND 8 groups and skipping calculation result from register output 2 to information output 20 of the device. The zero signal from the output of the element NOT 9 at this time closes the element And 10.

The operation of the device is prepared by setting the binary code of the monitored number at the input 21 of the device and the control module code at the device input 22 With the trigger signal applied to the device input 13, the switch 1 is set for the short time determined by the duration of the start pulse to 21 devices to the output of the switch 1. At the same time, a single signal is generated at the recording inputs of registers 2 and 3, and the number of the controlled number and the monitoring module are written on these registers venno. These codes are sent to the corresponding information inputs of the group 4 comparison units and the comparison unit 5. At the outputs Smaller than these blocks, a single signal is generated when the binary number at output 14 is less than the binary number from output 15 properly connected to the block (if you take the controlled number for K, and the control module for M, then in comparison block 4j the numbers K and Mx2J are compared, where 1 jk, where k is the number of comparison blocks in group 4),

When the size of the controlled number equal to n, the size of the control module equal to m, it turns out that k n - m.

The signals from the outputs of the comparison units 4 are fed to the decoder 12, which has the following truth table for case k 5.

The output 17 of the decoder 12 is fed to the control input of the multiplexer 7.

On subtraction blocks 6, binary values of the differences are determined. For j-ro block 6, the difference is determined

K-Mh2n.

The signals from the outputs of blocks 6 are fed to the information inputs 18 of the multiplexer 7. The code at the control input of the multiplexer 7 passes the smallest difference at K Mx2 to its output or a zero signal at K M.

On the first clock pulse, the first minimum difference is recorded in register 2 via switch 1. The process then continues until a zero signal is received from the output Less than block 5 of the comparison, indicating that the number on register 2 is less than the number on register 3 (the code of the control module). In this case, the remainder of the module is transmitted to the output 20 of the device through the elements AND of group 8. In this case, the zero signal from the output of the element NOT 9 prohibits the passage of the signals of the generator 11 through the element 10 to the input of the register 2 and the operation of the device ends.

A new cycle of works for the device O1 begins by applying new codes to the inputs 21 and 22 of the device and a trigger signal to the input 13 of the device.

If the condition K M is fulfilled when the device is started up, the contents of register 2 with the help of comparison block 5 are immediately transmitted to the output 20 of the device.

Claims (1)

Invention Formula A device for convolution by an arbitrary module containing two registers, a group of elements AND, a group of comparison blocks, a group of subtraction blocks and a multiplexer, the output of the first register connected to the inputs of the group being reduced, the output outputs of which are connected to the corresponding information inputs of the multiplexer, the information input of the second the register is the input of the device control unit setting, each i-th bit of the output of the second register is connected to the (i + j-1) -M bit of the first information input j-ro block group comparisons (1 im, where m is the control module's size, 1 j к, k nm, where n is the controlled number of the controlled number), characterized in that, in order to reduce hardware costs, the device contains a decoder, switch, comparison unit , clock generator, element NOT, AND element and element 5 OR, where the multiplexer output is connected to the first information input of the switch, the second information input of which is the information input of the device, the output of the switch is connected to the information input of the first register, the output of which is connected to the first information input of the comparison unit and the second information input of the group comparison blocks, output second register is connected with the second information input of the comparison unit, the output of which is less connected to the first inputs of the elements AND of the group and the input of the element NOT, the output of which is connected to the first input of the element AND, the output 0 which is connected to the first input of the OR element, the output of which is connected to the recording input of the first register, the second input of the OR element, the control input of the switch and the recording input of the second register are connected to the device start input, the output of the clock generator is connected to the second input of the AND element, outputs Less group comparison blocks are connected to the corresponding information inputs of the decoder, the output of which is connected to the control input of the multiplexer, each i-th digit of the output of the second register is connected to (i + j-1) -M bit minuend input house j-ro subtractor group, 5 bits of the output of the first register are connected to the second inputs of the corresponding elements AND groups, the outputs of which are connected to the corresponding bits of the information input of the device. 1vNJ6} 2 18c 16n1b # -116k-2 17 Phie.z / 8 / hl 18l1 FIG. 2 16l