SU1674350A1 - Controlled pulse generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automated control systems for digital devices. The aim of the invention is to improve the accuracy of operation of the controlled pulse generator by eliminating distortions of the pulse duration during restructuring or the end of generation. The purpose of the invention is achieved by introducing into the device the first D-flip-flop 1, the first 2 and second 3 AND-NOT elements, the second RS-flip-flop 4, the D-flip-flop 5, the comparison circuit 9, the AND 10 element, the counter 11, the driver 13 pulses, generator 14 reference pulses. In addition, the device contains a delay line 6, a multiplexer 7 and a register 8. Improving the accuracy of operation is achieved by synchronizing the switching time of the multiplexer 7 by a signal generated by the device. 1 il.

Description

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The invention relates to a pulse technique and can be used in automated systems for controlling digital devices as a source of pulses with programmed control of their period,

The aim of the invention is to improve the accuracy of operation by eliminating the distortion of the pulse duration during restructuring or the end of generation

The drawing shows a functional diagram of a controlled pulse generator.

The controlled pulse generator contains the first RS-flip-flop 1, the first 2 and the second 3 NAND elements, the second RS-flip-flop 4, D-flip-flop 5, delay line 6, multiplexer 7, register 8, comparison circuit 9, AND element 10, counter 11, output bus 12. shaper 13 pulses, generator

14 support pulses, bus 15 Reset bus 16 Period code, bus 17 Start, bus 18 Stop and bus 19 Record.

Bus 17 Start is connected to the S-input of the first RS-flip-flop 1, the inverse output of which is connected to the first input of the first element AND-NOT 2, the output of which is connected to the first input of the second element AND-NOT

3, the output of which is the output bus 12 of the device and connected to the second input of the first AND-NE element 2 and the input of the delay line 6, the outputs of which are connected to the information inputs of the multiplexer

7, the output of which is connected to the C-in / ode of the D-flip-flop 5 and the second input of the second element AND-NOT 3, Bus 16 The period code is connected to the information inputs of the register 8, the C-input of which is connected to the bus 19 Record and the S-input of the second RS trigger

4, the output of which is connected to the D-input of the D-trigger 5, the S-input of which is connected to the Start bus 17. The R-inputs of the second RS flip-flop 4 and D-flip-flop 5 are connected to the output of the comparison circuit 9, the first and second groups of inputs of which are connected respectively to the outputs of the register 8 and the counter 11. Bus

15 Reset connected to R-input register

8, the first R-input of the first RS-flip-flop 1 and the first input of the element 10, the output of which is connected to the R-input of the counter 11, the outputs of which are connected to the address inputs of the multiplexer 7. Bus 18 Stop is connected to the second R-input of the first RS-flip-flop 1. The inverse output of the D-flip-flop 5 is connected to the gating input of the multiplexer 7, the input of the pulse former 13 and the input of the reference pulse generator 14, the output of which is connected to the counter input of the counter 11. The output of the pulse former 13 is connected to the second input element I 10.

The controlled pulse generator operates as follows.

Multiplexer 7 is in a locked state, characterized by

a single signal at its output with a zero signal at its gating input, or (and) with zero signals at all its address inputs. On bus 15 Reset, a signal is applied that sets the signal to zero.

the state of the RS flip-flop 1, the register 8 and the element 10 of the counter 11. At the output of the comparison circuit 9, the signal O is generated, which sets the RS flip-flop 4 and D- the flip-flop 5. To

D-flip-flop 5 enters the gate of multiplexer 7 and allows it to work, but since the pulse counter 11 is in the zero state, signal 1 is present at the output of multiplexer 7.

Thus, the feedback of the generator, formed by element 3, delay line 6 and multiplexer 7, is open, and a signal with a unit level is present at the second input of the AND-HE element 3 and the C-input D of Figger 5. Since the RS-i rigger 1 is in the zero state, then the output of the element AND-NOT 2 contains the signal O, which blocks the feedback of the specified feedback, and the output of the element AND-NOT 3

Signal 1 appears. The signal received on bus 19 Recording, in register 8, the initial data on the duration of the period from the bus 16 are entered. Period code. Since the state of the register 8 has changed, a signal 1 is generated at the output of the comparison circuit 9, which sets the RS flip-flop 4 to 1 and prepares the device for operation.

With the arrival of a signal arriving at

Bus 17, the start, the RS flip-flop 1, the leading edge of this signal is set to one, and the output of the NAND-2 element appears on signal 1, which prepares the aforementioned feedback for operation and leads to the appearance of O on the output of the I- NOT 3, which marks the beginning of the pulse sequence generation process.

The same signal translates the D-trigger 5 into

single state. The signal from the inverse output of this trigger enters the gate of the multiplexer and blocks it. This signal also includes a 13-pulse back-turn and 14 reference oscillator.

pulses. The pulse generated by the shaper of 13 pulses, the leading edge through the element And 10 confirms the zero state of the counter 11. The duration of this pulse must be less

the duration of the half-period of the generator is 14 reference pulses, the period of which is 0.5 T0, where T0 is the period of the device's pulses, determined by the signal delay on one Even line 6 of the delay.

After confirming the zero state, the counter 11 starts counting the pulses of the generator 14.

At the moment when the state of the counter 11 becomes equal to the state of register 8, the output of the comparison circuit 9 is the output signal O, which is overpowered and the RS triter 4 and O path state is triggered 5, prohibiting the operation of the generator and simultaneously unlock the multiplexer 7 at the input of a grabirolani. Thus, during the time t, crmeein) is 0.5T0 t 1T0, in-mail feedback to the work, including the first line of delay line 6. On the output bus 12, the voltage is generated; the sequence of pulses with a period of de i is the number of links of the delay line 6 determined by the period code recorded in register 8

When the bus enters 16, the code of the period for the data of the period code last after the signal is input to the bus / Record is written in pei-hstr 8. With the last change of the output signal of the comparison circuit 9, the signal 1 is generated. The same signal from the bus 19 Record RS flip-flop 4 is set to one state, prepared by D-input D-flip-flop 5, and, when the feedback circuit formed by the l-th link of delay line 6, at the first input of the element HE NOT 3 and the C input of the trigger ъ voltage will be transferred from state O to state 1, i.e. the previous period completely formed, the D-flip-flop 5 is set to one and the feedback loop is repeated including the je link of the delay line b, and the device will generate pulsed pulse with a period of T j. Where J is the number of links of the delay line 6 determined by the new period code recorded on register 8

The process of generating pulse sequences with a certain period of duration continues until a signal is received on the Stop bus that sets RS-trigger 1 to zero. Thus, the O signal at the first input of the AND-NOT 2 element stops. If the last pulse of the sequence has not yet been formed, i.e., the signal O does not yet remain at the output of the second element AND-HE 3, then the click signal formed by the ring circuit of elements AND-HE 2 and 3 will not work.

ready when the steady pulse of the series is fully formed, that is, when the first input of the i-HE 3 element has a G signal. If at the moment of transition to the RS state of the trigger 1 the last pulse of the sequence on the output bus 12 b / d , then the latch will work immediately

Thus, the invention allows r, f to form the previous period, about the first impulses of the pulse of the period and the pistons of the period of the control generator, which guarantees the accuracy of the last for the comparative ( with device gg

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Claims (1)

Invention Formula Managed pulse generator, which contains the register information inputs of which are connected to the bus Period code, multiply K (, op and line chaderzh The bridges that are connected to the MY / Biplex data inputs, are characterized in that, in order to improve the accuracy of the work of the JR c, the distortion of the signal or the end of the generation has been eliminated; the second RS flip-flop, per-1ZyG and the second elements of the I-ME, P-flip-flop comparison, element I, forma- tion, e it impulses, g) snex) ator reference impulse5 LOB and the counter 5-input D-flip-flop is connected to Start and S - to the input of the first PS-trigger; pd whose inverse output is connected to the first input of the first NAND element, the output of which wow connected to the first input 0 of the second NAND element, the output of which is a satellite bus, device and connected to the second input of the first element AND NOT and the input of the holdback line, the output of the multiplexer is connected to the second input of the second element NAND and C-A of the D-trigger, D - the input of which is connected to the output of the second RS-flip-flop, the S-input of which is connected to the bus Record and the C-input of the register, the outputs of which are connected to the first group of inputs of the comparison circuit, the output of which is connected to the R-inputs of the second RS-flip-flop and D- trigger, the inverse output of which is connected to the inputs of the trigger l reference clock pulse generator and the entry 5 gates of the multiplexer, the address inputs of which are connected to the second group of inputs of the comparison circuit and the outputs of the counter, the counting input and the R input of which are connected respectively to the outputs of the reference pulse generator and the And element, 716743508 the first input of which is connected to the bus; pogo is connected to the stop bus; the output is Reset and the R input of the register and the first R input, the pulse former is connected to the second of the first RS trigger, the second R input of which input I.