SU1661752A1 - Multifunctional logic module - Google Patents

Abstract

The invention relates to computing and can be used in the construction of multifunctional digital information processing devices and industrial automation units. The purpose of the invention is to simplify the multifunctional logic module when calculating symmetric Boolean functions. The module contains the element OR 1, the shift register 2, the demultiplexer 3, the encoder 4, the block 5 for calculating elementary symmetric Boolean functions, trigger 6, the element AND 7, the counter 8. The binary information variables X ₁ , X ₂ , ... , X _N , and the binary code ϕ (F) of the implemented symmetric Boolean function F = F (X ₁ , X ₂ , ..., X _N ) is entered into the shift register. During the N + 1 clock cycle, the output of the module realizes the value of the function F defined by the binary code ϕ F. 1 Cp f-crystals, 1 tab., 2 ill.

Description

eleven

13

1l

/four

0-1

oh oh

vi ate yu

figure 1

The invention relates to computing and can be used in the construction of multifunctional digital information processing devices and industrial automation units.

The purpose of the invention is to simplify the multifunctional logic module when calculating symmetric Boolean functions (SBF).

Fig. 1 shows the block diagram of the multifunctional logical module J in Fig. 2, a functional diagram of a unit for calculating elementary SBF (ESBF) included in the module.

The module contains the element OR 1, the shift register 2, the demultiplexer 3, the encoder 4, the ECGF calculation block 5, the trigger 6, the AND 7 element, the counter 8, the group of information inputs 9, the configuration input 10, the first 11 and the second 12 inputs of the module reset respectively, clock input 13 and output 14.

The ESBF calculation block contains n EXCLUSIVE OR elements (n is the number of arguments of ESBFs being audited) 1 majority element 16 with threshold n, major element 17 with threshold n + 1 (has only inverse output), element I 18, n information inputs, n-1 tuning inputs 20 (-20.1.1, prohibition input 21 and output 22.

The module works as follows.

It is known that arbitrary SBF n arguments F F (X, X „, ... can be uniquely represented as

V

F fix vfr

n

Fnv

(one)

and i

where - elementary (or fundamental) SBF from n arguments, 1tsЈ {0,1J

Thus, there is a one-to-one correspondence between SBF F F (Xp X, ..., Xn) and (n + 1) -disable binary code / IT (F) (1Г0 /

ъ

g

,, ...

 P

From (i) it also follows that

F - MF,

where the disjunctions is taken for all of which 1GK 1,

(2) K, DL

Since all ESBF F are mutually

op

0

five

0

five

0

then, on a given set of binary variables X (, X,, X, the value of a logical unit takes no more than one ESBF from the set RM "Therefore, to calculate an arbitrary SBF (Xf, X2 ,, .., X) from and the arguments X", X ", ..., X, defined by its binary code 1 (F), we can propose the following procedure: calculate successively the values of the ESBF from fFhjHa to the given set of arguments X, X, ..., CP to obtain a single value and then F 1 on this set, or until complete enumeration of all ESBPs from fFnV and then F 0, since all the terms on this set are in (2) they are equal to zero. The module contains a shift register 2, into which the code "(F) implemented by the SBF FF (X ,, Xg, ..., Xn) is entered. Through the demultiplexer 3, the value of the most significant bit of register 2 is the value of the next component The binary code 1TTj (F) controls the operation of the encoder 4, which forms the setup code of the ESBP calculation block 5: if / | G 1, the encoder 4 sets up block 5 to calculate the function F | J whose value on this set is fixed in trigger 6, if and | 0 ,. the operation of the encoder 4 and subsequent nodes is blocked. Then, in the shift register 2, a ring shift of information by one bit is performed and a similar component analysis is performed; . The operation continues either until all the components of the binary code T (P) are iterated, if F 0 on the given set of arguments

five

cops X

HP, either to the floor

A single value of the function stored in trigger 6. At the same time, the signal from the inverse output of trigger 6 prohibits receipt of clock pulses through element 7 at the input of the module and indicates the completion of the calculation of the F value on this set. Counter 8 in the process of work indicates the number of the analyzed component T ;,

Multifunction logic module works as follows.

Before starting, pulses are supplied to the first 11 and second 12 inputs of the module reset, which zero the shift register 2, the trigger 6 and the counter 8. Next, the module is tuned to the SBF implementation

5166

FF (X4, X, ..., Xn) given by its binary code T (F) („, Iff, H 2. / C) accompanied by a series of n + 1 clock pulses fed to clock input 13, per input 10 settings are received sequentially from the components of 1G0, (,, ...,. ../| G ". As a result, Kofan iTCF is recorded in the (n + 1) -th bit of the shift register 2), and in the higher bit connected to the input of the demultiplexer 3, the prohibition input of the ESCF calculation unit 5 and the input of the element OR 1, the value 1Г0 takes place, and in the youngest - the value IT. The counting module of the counter 8 is equal to n + 1. Obviously, the counter size is equal to r J + 1), therefore, after the indicated series of n + 1 clocks are delivered, the counter 8 goes back to zero state, the code of which indicates the binary number of the component 1 of the vector IT (F) connected to the input of the demultiplexer 3. Since the counting input of counter 8 is connected to the clock input of the shift register 2, the r-binary code i of the state of the counter 8 always indicates the number of the component that is at the moment de shift register 2. After s Shift code (P) to shift register 2 module is ready for operation. The binary arguments X., X, ..., are supplied to the buses of the group of information inputs 9 of the module.

   fi

During the (n + 1) -th clock cycle of preparing the module for operation, trigger 6 is in the zero state and a single signal from its inverse output supplied to the input of the AND element allows the passage of clock pulses from clock input 13 to the clock input of the shift register 2 and counting input counter 8. This. is provided by the fact that when entering the shift register 2 of code ii (F) at the input of the prohibition of the ECGF calculation block 5, there is a high-order signal of the preset zeroed shift register 2. This zero signal prevents the formation of a logical unit signal at the output of the block 5 during preparing the module for work,

Demultiplexer 3 has n + 1 output (from zero to nth), one infor752 6

a mating input associated with the high-order output of the shift register 2, and g + l) address inputs, which receive signals from the corresponding bits of counter 8. In this case, with a circular shift of information in the shift register 2 in the process of calculating SBF FF (X ,,

0 ft) B high order, the components 1G D,, ...,%, 1Г0, if,, ... are consistently present and, thus, the values of these components in the same sequence have

c place at the outputs of the demultiplexer 3: zero, first, ..., nth, zero, first, etc.

Unit 5 of calculation of ESBF has n information inputs for which

The 20 information inputs of the 9 modules come in parallel with binary variables Xj, Xg, ..., Xn implemented by the SBF F F (X ,, X, ..., Xh), and n-1 of the configuration inputs to which

1.2

25 code settings V (U ,, U

..., U; M,) from the outputs of the encoder 4, where i 6, 1, ..., n; in {О, 1 and S 1, 2,.,., p-1. The functions of the encoder 4 are to transform

The signal of a logical unit at the ith input (, 1,., .., n) is in (n-1) is the bit vector V at the output. Therefore, encoder 4 has n + 1 inputs and n-1 outputs. Since the outputs of the demultiplexer 3 are connected to the corresponding inputs of the encoder 4, at the same time no more than one signal of a logical unit can act on the inputs of the encoder, therefore always

The lp will be a one-to-one correspondence between the / ir 1 signal, acting on the 1st input of the encoder, and the vector V, which configures unit 5 to calculate the ESBF P n (i 0, 1n).

45

In the initial state in the senior

the bit register of the shift register 2 is the component 1GV of the vector (F), the counter 8 is reset. At zero you- 5 (during demultiplexer 3 there is also a 1Г0 signal.

If / th () 1, the encoder 4 generates

Vj tuning vector (UB (t, U0 (2

 about VM tuning | and Spock 5 on the implementation of the function F °. The value FЈ on this set of arguments X ,, X, ...., Chl from the output of block 5 is fed to the information input of trigger 6. On the leading edge of the first sync

The pulse of the work series received at the clock input of the 13 module, the value of F6 is written to the one-step, ..., trigger about (. such

a trigger can be selected, for example, a synchronous D-trigger). If a

w

Fu 1 on this set of arguments, and consequently F F (X ,,, X, ..., x “) 1 on this set, the signal from the inverse output of trigger 6, further input of clock pulses to clock input 13 is blocked. The value of the implemented function F is equal to a logical one and is fixed in trigger 6.

If O (ESFP F® is not included in (k) or F ° 0 on this set), then on the leading edge of the first working clock pulse, the zero state of flip-flop 6 is confirmed if / Stn 1. then the value of the most significant bit

The dvig register 2 supplied to the inhibit input of block 5 will block the efo output signal.

In both cases, or / 0

  one)

on the falling edge of the first sync pulse in the shift register 2, an annular shift of information occurs (in the high bit the value j is written, in the low bit (Go), and the state of the counter 8 will increase by one and indicate the component number, the vector iT (F), At the moment, at the first output of the demultiplexer 3 there is a signal and at 1 encoder 4 sets block 5 to implement the function F

If, after filing the first working clock pulse, trigger 6 remains in the zero state, the next work clock pulse is applied, on the leading edge of which the trigger F is written to the value F on the given set of arguments X, X0, ..., X (with 1), or zero is confirmed trigger state 6 (when, if. 0). On the falling edge of this clock pulse, a circular shift of information in the shift register 2 and an increase in the content of the counter 8 by one are also performed. If, after the second clock cycle, trigger 6 remains in the zero state, a third sync pulse is applied, on the leading edge of which the trigger EFB F on this set is entered in trigger 6 (with

  1) or the zero state of the trigger is confirmed. On the falling edge of the sync pulse, there is also an annular shift of information in shift register 2 and an increase in the content of counter 8 by one.

The calculation of the SBF FF value (X4, X, ..., X) on this set of arguments continues either until a single value is fixed in flip-flop 6 (this indicates that F 1 is on this set of arguments) or until the end of the working series of n + 1 clock pulses applied to clock input 13. In the latter case, the value of F is determined by the state of flip-flop 6 after the end of the (n + 1) -th clock pulse.

Q To calculate the value of a given SBF F F (Xf, Xz,.,., X) on a new set of arguments, the information inputs of the 9 modules are supplied with new values of the arguments X, X, ..., X,

5, trigger 6 is zeroed by applying a pulse to a second reset input 12, and the next working series of n + 1 clock pulses is applied to clock input 13 (successive impulses per pulse from 0, either to fixation to trigger 6 of a single value, or to the end of the entire series pulses)

If the value (X, X ,, .., X | J was calculated ahead of time (the unit value of F was recorded in the trigger .6 for 1 t "cn + 1 clock pulses), there is no need to end the current series of n + 1 working clock pulses Trigger 6 is zeroed out, and the new value of the arguments Xj, X, ..., Xw is followed by the next series of clock pulses. In this case, obviously, the analysis does not begin with the component

functions F with o.,

that U-t (and the corresponding function at 11 c. 1). Thus, the average computation time of the SBF (X, Xg, ..., ..., Xn) will be

 And o (and corresponding V o,

and with component (pn) l about;

(3)

where v is the period of clock pulses.

The tuning codes Vm (U.,. ,, U; 2, U ;,) and the corresponding realizable ESBF F (i О, 14) for

block 5 (Fig. 2) with n 4 are presented in the table (the value of the signal on

the input 21 of the ban is equal to this logical unit).

As follows from Figures 1 and 2, the value 21 of the component of the output of the high bit of the shift register 2 arrives at the prohibition input 21 of the ESBF calculation block 5. Obviously, if fr; 0, then, in accordance with (2), the value of F on this set of arguments X ,, X, ..., ..., Xn is ignored due to the occurrence of a zero signal at output 2 of block 5 connected to the information input of trigger 6.

The structure of the encoder 4 is considered on the example for Clause 4. For this, we use the table of settings of block 5

Let us introduce the following notation: let a be the signal at the i-th output of the multiplexer 3 (and respectively at the i-th input of the encoder 4), bj is the signal at the j-th output of the encoder 4 connected to the tuning input of block 5, where, 1 , ..., 4 and j 1, 2, 3.

20;

As follows from the table of settings

a 0V a, V a,

ii

 agu a

Thus, as follows from (4), with n 4, the encoder 4 consists of two OR elements with three inputs each.

If we take into account the orthogonality of the signals at the inputs of the encoder 4, then

B (af, b. A.

2

Le a0V (5) it follows that the encoder 4 can also be built on the basis of two two-input elements OR NOT.

An additional positive effect of the invention is a higher response rate.

Claims (2)

1. A multifunctional logic module containing a counter, a shift register and an OR element, the first input of which is connected to the module settings input, the output of the high register shift register is connected to the second input of the OR element, output 2 ten 15 661752 About which is connected to the low-order input of the shift register, the installation input to Oh which is connected to the installation input to the counter O, and the first reset input of the module, which, in order to simplify the calculation of symmetric Boolean functions, contains a demultiplexer, encoder, unit for calculating elementary symmetric Boolean functions, trigger and AND element, clock input of the module connected to the first input of the AND element, the second input of which is connected to the inverse output of the trigger, output of the AND element connected to the counting input account Ica, p. the clock input of the trigger and the clock input of the shift register, the high-end output of which is connected to the inhibit input of the computation block of elementary symmetric Boolean functions and the information input of the demultiplexer, the address inputs of which are connected to the counter outputs the tuning inputs of the computing unit for elementary symmetric 3Q boolean functions, the information inputs of which are connected to the information inputs of the module, and the output The one is connected to the information input of the trigger, the installation input to O of which is connected to the second input of the module, and the direct output is connected to the output of the module. 20 25 35 40 2. Module pop.1, which differs from the fact that the block for calculating elementary symmetric Boolean functions contains the element AND, the majority element with the threshold n (n is the number of arguments of the elementary symmetric Boolean functions that are implemented), the majority element with the threshold The PI and n elements EXCLUSIVE OR, the first input of the i-th (i 1, 2, ..., p) of which is connected to the i-th information input of the block, the second input is connected to the first tuning input of the block, and the output is connected to the i-th input of the majority element with a threshold n and the i-th input of the majority element with a threshold of n + 1. (n + j) -and (, 2, ..., p-2), the input of which is connected to the (j + D-m tuning input of the unit and (II + J) -M input of the majority element with threshold n, the output of which is connected to 50 the first input element And, the second input of which is connected with the inverse output of the majority element with a threshold of n + 1, X2 XB X4 1OO 101 111 O01 000 five the block inhibit input is connected to the third input of the AND element, the output of which is connected to the output of the block. - X1 X2 Y5 4 X, XZX, X XjXgXyV X (HgHyX V X Chl X l.  X, X2. V X, XaJf, X X, X2. V X, X4X5X.V X,  X (X2X, X + UH, HgHeH4U XtX2XjX4V vx, Х1ХГххх4 Ha dl.6 18 122