SU1658104A1 - Filter - Google Patents

Abstract

This invention relates to radar. The purpose of the invention is to enhance the functionality by filtering the complex signal. The filter contains switches 1-6, lines 7 and 8 delays, inverters 9-11. integrators 12 and 15, control block 13, clock generator 14, gating blocks 16 and 17, low pass filters 18 and 19, and trigger 20. Functional expansion is achieved by processing complex samples of the signal 3 Il.

Description

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The invention relates to radar and can be used in devices detecting complex signals for optimal filtering.

The purpose of the invention is to enhance the functionality by filtering the complex signal.

Figure 1 shows the structural electrical circuit of the proposed filter; 2 shows a control unit; Fig. 3 shows timing diagrams for removing filter operation.

The filter contains the first 1, second 2, third 3, fourth 4, fifth 5 and sixth 6 switches, delay line 7, additional delay line 8, inverter 9, first and second additional inverters 10 and 11, integrator 12, control unit 13, generator 14 clock pulses, additional integrator 15, gating unit 16, additional gating unit 17, low-pass filter 18, additional low-pass filter 19 and trigger 20, control unit 13 contains a reversible counter 21, a decoder 22 zero, an address counter 23, a decoder 24 number weights s and a block 25 fixed memory.

The filter works as follows. The signal to be filtered comes in the form of samples of the real and imaginary components (quadrature components) to the second (signal) inputs of the first and fourth switches 1 and 4, which for a time equal to the period of the clock pulses (Fig. For) generator 14 clock pulses, There are second inputs of the first and fourth switches 1 and 4, respectively, with the input of the delay line 7 and the input of the additional delay line 8. The first and fourth switches 1 and 4 are controlled by a signal (Fig. 36), coming from the output of the control unit 13. At the same time, the integrator 12 and the additional integrator 15 are reset and the trigger 20 is set to the zero initial state. After recording the reference signal of the complex signal to the delay line 7 and the additional delay line 8 at the time Tt (FIG. 3B-n), the first and fourth switches 1 and 4 switch and the output of the delay line 7 and the additional delay line 8 are connected via the first and fourth switches 1 and 4 with their inputs, which ensures a recirculation shift in time of the samples of the complex signal. The shift control in the delay line 7 and the additional delay line 8 is carried out by pulses arriving at the clock inputs of the delay line 7 and the additional delay line 8 from the output of the trigger 20, and the shift occurs along the negative edge of the pulses (Fig. Sv). On the time interval Ti - T0 (Fig. Zn-n)

the input signal samples are recorded, which are recorded on delay line 7 and an additional delay line 8, equivalent to filtering the complex signal.

The first filtering phase occupies the time interval Ti − T2, and from the constant memory unit 25, the code of the real component of the first complex coefficient (1) is read. Then in

control block 13, this code is converted into a time interval proportional to QReO)

Tfce (1) igRe (D | At, where Tfoe (1) is the time interval until the next impulse control unit 13 appears at the output of the control unit 13;

At- period of the clock pulses of the generator 14 clock pulses.

On fig.Z the case of dke (1) 2 is given.

Due to the fact that the bottom (1) is positive (Fig. SID), the third and sixth switches 3 and 6 connect the outputs of the second and fifth switches 2 and 5 to the inputs of the integrator 12 and the additional integrator 15, respectively, without inversion and during the time Tfce (1) the real and imaginary components of the first signal are integrated. As a result, at t T2, the voltage at the output of the integrator 12 has the following form (Fig. 3k):

. () - s "-0) e | S0) s". (one)

ABOUT)

where YRe (1) is the voltage at the output of the integrator 12;

gi - integrator integration constant 12;

SRe (1) is the real part of the first off-signal signal.

At the output of the additional integrator 15, the voltage is

50

Y.4i) isi-Ci)) - (Mi) Su. (1)

t

where Sim (1) is the imaginary part of the first reference signal.

At the moment of time t T2. The switching of the counter 23 of the address occurs and the imaginary part of the complex factor gim (1) is read (in Fig. Sv gim (1) -1). switches three and sixth switches 3 and 6 (since the sign of gim (1) is negative)

and the state of the trigger 20 is reversed. The second switch 2 connects the output of the additional delay line 8 via the first additional inverter 10 to the input of the inverter 9, and the fifth switch 5 connects the output of the delay line 7 to the input of the second additional inverter 11. The third and sixth switches 3 and 6 connect the outputs of the second and five switches 2 and 5 with inputs of integrator 12 and additional integrator 15 through inverter 9 and second additional inverter 11, since the next weighting factor is gim (1) -1 (Fig. Ze, h, gi).

During the time interval T2 - Tz, the integration of Sim (1) and 5р (1) takes place. Since the integral of the sum is equal to the sum of the integrals, taking into account formulas (1) and (2), the voltage at the outputs of the integrator 12 and the additional integrator 15 has the form

YR. (2) gR, (l) 5 ". (1) + 9i4) Si -. (T) j Vi (J) Ј gn. () Si" (1) - | "(1) Sn. (1 )

Thus, in the interval TI - Tz, the complex multiplication of the first complex sample of the filtered signal S (1) is performed by the first complex filter coefficient g (1):

about d. about about

) g (i).

(five)

Gi

At t T3, the address of the block 25 of the memory is switched and the code of the real component of the QRe coefficient (2) is read. At the same time, in the delay line 7 and the additional delay line 8, there is a recirculation shift of the signal samples by one clock cycle, and a second sample of the 5 e (2) signal appears at their outputs. In the time interval Tz - T ", the multiplication S (2) by g (2) is performed. Similarly, the sum of products is formed on the interval TI - T0

At

4 o

(6)

Y-f .JSOW).

At the time t T0, the integration results are transmitted through the gate unit 16 and the additional gate unit 17 to the input of the filter 18 and the additional low-pass filter 19 and the integrator 12 and the additional integrator 15 are reset. Filter 18 and the additional filter 19 are reset

Claims (1)

low pass allows interpolation of the response of the proposed filter. In the constant memory block 25, the weighting coefficients are written in the following sequence: dk «(1), gim (1). Dre (2), gim (2), etc., moreover, n bits are reserved for the coefficient module, and (n + 1) -th bit carries information about the sign of the coefficient. Invention Formula 10. A filter comprising a clock pulse generator, a control unit and a serially connected first switch, a delay line, a second switch and an inverter and a serially connected input block, a strobe unit and a low pass filter, the output of the delay line connected to the first input of the first switch, and the output The clock generator is connected to the input of the control unit 20. the output of which is connected to the control inputs of the first switch, the integrator and the gating unit, which is characterized in that. In order to expand the functionality by filtering the complex signal, a trigger, a first additional inverter, a third switch and a fourth switch connected in series, an additional power line 30, a fifth switch, a second additional inverter, a sixth switch, an additional integrator, an additional gate unit and an additional a low-pass filter, with the output of the inverter In35 connected to the first input of the third switch, the output of which is connected to the integrator input, output d of the second switch is connected to the second input of the third switch, the output of the additional line The delay 40 is connected to the first input of the fourth switch and the input of the first additional inverter, the output of which is connected to the second input of the second switch, the output of the delay line is connected to the second input of the fifth switch, the output of which is connected to the second input of the sixth switch, the output of the control unit is connected to the installation the trigger input, the control inputs of the fourth commutator, the additional integrator, and the additional gate unit; the first additional output of the control unit is connected to the control yuschimi inputs of the third and sixth switches, the second 55, the auxiliary output of the control unit is connected to the counting input of a trigger, the output of which is connected to the control inputs of the second and fifth switches and the clock inputs of the delay line and the auxiliary delay line.