SU1649579A1 - Device of power supply interruptions - Google Patents

Abstract

The invention relates to power supply automation equipment and can be used in power supply networks and directly with electrical power consumers. The purpose of the invention is to increase the resolution and accuracy of the device. The device contains a sensor 1, a differentiation unit 2, a pulse generator 3, a counter 4, reversible counters 5 and 11, decoders 6 and 8, a multiplexer 7, a control unit 10, an operational storage unit 12, a bus driver 13, an OR unit 14 and a block 9 indications. The resolution of the device is determined by the time of writing information to the operational storage unit 12, which is seven clock periods. 1 il. about "

Description

The invention relates to equipment for the automation of power systems and can be used in networks of power systems and directly from consumers of electrical energy.

The purpose of the invention is to increase the resolution and accuracy of the device.

The drawing shows the block diagram of the device.

The device contains a sensor 1, a differentiation unit 2, a generator of 3 pulses, including a quartz pulse generator and a frequency divider, counter 4, containing, for example, six bits: minutes, hours and days (two digits in each dimension), the first reversible counter 5, the first decoder 6, the multiplexer 7, the second decoder 8, the display unit 9, the control unit 10, the second reversal counter 11, the operational storage unit 12, the bus driver 13 and the unit 14 of the OR elements.

In the initial state, the monitored voltage is turned on, at the output of sensor 1, the signal corresponds to 1. Counter 11 is in the polling state of the initial address of block 12. Block 10 is in the initial state corresponding to the information storage mode in block 12. In this mode, From the second outputs of block 10, the Sampling signal is sent to the control inputs of block 12 and bus drivers 13, which prohibits the exchange of information between them (they are interconnected by two-way communication buses), from the first output of control block 10 and the control input of the multiplexer 7 is fed a signal permitting transmission through the multiplexer 7, the current time from the counter 4 via unit 14 to a decoder 6, A with its outputs to the display unit 9. This information is transmitted in bits (in this case, six bits, n 6) in a parallel binary-decimal code for each binary digit. The decoder 6 converts the signal of a binary-decimal code into the digital code of the display unit 9, for example, a decimal seven-segment signal. This bit polling is performed using counter 5, which continuously switches from the first to the last (seventh, n + 1) state and back. Decoder 8

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converts the binary signals of the counter 5 into the decimal code, which are fed to the third inputs of block 9. Thus, the first inputs of block 9 receive sequentially information signals of each bit, and the third inputs - sequentially signals of the number of the displayed bit. This provides a dynamic mode of operation of block 9. A generator of 3 pulses generates two sequences of clock pulses fr and f.J, (f-J- are shifted relative to fT), as well as pulses f {time counting with a period of, for example, 1 min delayed relative to the corresponding pulses f. The change in the counting direction of the counter 5 is carried out by the block 10 when the signals from the first input to its fifth input and from the sixth input of the decoder 8 to the sixth input. The counter 5 switches with the clock frequency fr, which comes from the third outputs of the block 10 to the counting inputs addition at the counting from the first to the seventh state and to the inputs of the subtraction at the counting from the seventh to the first state. The minute pulse f is also fed to the fourth input of the unit 10 and to the installation input of the counter 5 to synchronize their operation in various modes. The signals from the first outputs of the counter 1 1 in binary code go to the second inputs of block 9, in which they have their own indicator to indicate the address of the polled block 12.

When the monitored voltage is turned off at the output of sensor 1, O is set, and a single signal appears at the output of block 2, which sets block 10 to the state of recording information of counter 4 into block 12.

At the same time, the control inputs (first inputs) of block 12 and bus formers 13 from block 10 receive the Allow Sample and Record signals that allow the transmission of information from counter 4 through multiplexer 7 and bus drivers 13 to block 12. At the same time, the clock pulses fT coming from one of the fourth outputs of block 10 to input +1, the counter 11 switches. This switch occurs synchronously with the switch of counter 3. Thus, information is recorded in block 12. Recording stops when the signal arrives seventh exit

decoder 8. In this case, block 10 is set to its initial state, block 12 and bus drivers 13 are closed, and counter 11 is set to the starting address state of the next information record.

When the monitored voltage is turned on, the output of sensor 1 is set to 1, and a single signal appears at the output of block 2, which sets block 10 to the state of recording information from counter 4 to block 12. The device then works in the same way as when the voltage was turned off .

According to the status of the address counter 11 indicated by the display unit 9, it is possible to determine the number of trips and on.

If the starting address of block 12 corresponds to the zero state of counter 11, then the number of measurements M (at six bits) is determined by the formula

N,

where n is the state of the counter 11.

The even values of N correspond to the off time and the odd ones to the turn on time of the voltage.

When counter 11 overflows (and, correspondingly, the capacity of block 12), the signal from its second output goes to the seventh input of block 10 and sets the Sampling block of block 12 mode. This ensures that information previously recorded in the lower bits of block 12 is saved, since the overflow of the counter 11 will again start from the beginning of the address of the block 12.

Information output from block 12 to block 9 is performed by setting block 10 to read mode. The signal from one of the fourth outputs of the block 10 is fed to the input of Set. O and the counter 11 is set to the initial state, and the control inputs of the block 12 and bus drivers 13 from the second outputs of block 10 receive signals allowing information transfer from block 12 via bus drivers 13 and the decoder 6 to block 9, and to the control the input of the multiplexer 7 receives a control signal prohibiting the transmission of information from counter 4 through multiplexer 7. Information from block 12 via bus0

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The shaper units 13, block 14 and decoder 6 are output bitwise. the first inputs of block 9. On the third input |. The units of block 9 are successively received from the outputs of the decoder 8, the signals are the number of the ra of the displayed bit. In read mode, counters 5 and 11 synchronously switch: counter 5 - from the first to the last (seventh) state, and counter 11 addresses from the starting address, for example zero, to the sixth, and then in the opposite direction, etc. This provides the output of the first measurement information in a dynamic mode. The display time is determined by the operator. At the end of the indication mode of the first measurement, the counter 11 is set by block 10 to the starting address of the next measurement, and the block 10 itself is set to the information storage mode in block 12. The operator switches on 10B to the mode of polling the information of the second measurement. At the same time, the information is output in the same way as described. At the end of the second measurement indication mode, the counter 11 is set to the starting address of the next measurement, and the control unit 10 itself is set to the information storage mode in unit 12. The eating measurement results are output from the unit 12 to the display unit 9 in the same way.

Thus, the resolution (the minimum time between turning off and turning on the monitored voltage) of a device is determined by the time of recording information in block 12, which is seven periods of clock pulses. The minimum clock period is determined by the speed of the selected element base. Therefore, it is possible to build devices for monitoring power interruptions in a wide range of resolution, which makes it possible to use them to control the speed of switching equipment and protection devices

Claims (1)

Invention Formula Device for monitoring power interruptions, containing a sensor, a block of elements OR, a counter 9, a first decoder, the pulse generator of the first and second outputs of which are connected to the first and second inputs of the block control and display unit, characterized in that, in order to increase the resolution and accuracy of the device, an operational storage unit, a bus driver, a second demirator, a multiplexer, first and second reversible counters, and a differentiation unit are inputted to the output of the sensor and the output is with the third input of the control unit, the fourth input of which is combined with the installation input of the first reversible counter and connected to the third output of the pulse generator, which is connected through the counter a first data input T UCHM COpJ} OUTPUT which is connected to informational and inertial and generator and block, OR elements, the output of which through the first decoder is connected to the first input of the display unit, the first and second outputs of the control unit are connected respectively to the control input of the multiplexer and to the control the inputs of the operational storage unit and the tire driver, the outputs which is connected to the second input of the OR unit, the bus driver's input-output is connected to the operational storage unit's input-input, whose information input is connected to the first output of the second reversible counter, which is connected to the second input of the display unit, the third outputs of the control unit are connected respectively to the input addition and with the subtracting input of the first reverse counter, the output of which is connected to the second information input of the multiplexer and to the information input of the second decoder, the first to sixth outputs of which are connected to the third input of the display unit, the fourth outputs of the control unit are connected to the addition input, the subtraction input and the installation input of the second reversible counter, the second output of which is connected to the seventh input of the control unit, the fifth and sixth inputs of which are connected respectively to the first and the seventh output of the second decoder.