SU1492328A1 - Device for automatic testing of electric power meters - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to simplify the device by simultaneously monitoring the permissible error of all the inverted electricity meters by determining whether the counter values of 6 clock pulses of each counting channel 1 are within the tolerable range using digital comparators 26 and 27. All counting channels 1 are sampled by multiplexer 22, and To match its information inputs with the information outputs of the demultiplexer 23, a counter 24 serves. According to the operation of the signaling device 30, it is judged that the error is verifiable go counter is valid. The drawing also shows a photo sensor 2, a pulse generator 11, a frequency divider 12, a channel selection unit 13, memory blocks 16 and 18, a control panel 15, display units 14, 17, 19 and 20. 1 il.

Description

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of each channel 1 within the range allowed by the UOMOQIH digital comparators 26 and 27. All channels 1 of the account are polled by the multiplexer 22, and to match its information inputs with the information outputs of the demultiplexer 23, a counter

 1A92328

the operation of the alarm device 30 is judged to ensure that the accuracy of the counter being tested is acceptable. The drawing also shows a photo sensor 2, a pulse generator 11, a frequency divider 12, a channel selection unit 13, memory blocks 16 and 18, a control panel 15, display units 14, 17, 19 and 20, 1 slug.

The accuracy of the verified counter is valid. The drawing also shows a photo sensor 2, a pulse generator 11, a frequency divider 12, a channel selection unit 13, memory blocks 16 and 18, a control panel 15, display units 14, 17, 19 and 20, 1 slug.

The invention relates to a pulse technique and can be used when calibrating electricity meters. The aim of the invention is to simplify the device by using one block of simultaneous control over the permissible error of all inverters 4 Ix electricity meters. The drawing shows a structural-functional diagram of the device.

The device contains n channels 1 of the account, each of which includes a photo sensor 2, the first element I 3, the inverter 4, the counter 5 input pulses, the counter 6 clock pulses, the second element I 7, the trigger 8, the decoder 9, the multiplexer 10, and contains a pulse generator 11, a frequency divider 12, a channel selection unit 13, a first display unit 14, a control panel 15, a first memory block 16, a second display block 17, a second memory block 18, a third display block 19, a fourth display block 20 and block 21 of simultaneous control over the permissible error of all ep ekyh energy meters, including a multiplexer 22, a demultiplexer 23, a counter 24, a first OR element 25, the first 26 and second 27 digital comparators, AND gate 28, the second OR element 29 and the n sensors 30,

At the same time, the output of the photo sensor 2 in series AND 3 elements, inverter 4, counter 5 input pulses, decoder 9 and multiplexer 10 are connected to the inputs of elements 3 and 7, the output of element 7 7 is connected to the counting input of the counter 6 clock pulses the one of which is connected to the resolution enable input of the counter 5 input pulses and to the output of the trigger 8, the first input of which is connected to the output

Inverter 4, the second inputs of the trigger 8 of all the counting channels are connected to the output of the control console 15, the outputs of the counters 6 clocks of all the counting channels are connected to the inputs of the channel selection unit 13 and the multiplexer 22, the outputs of the multiplexers 10 of all the counting channels are connected to the inputs of the element OR 25, the inputs of the elements AND 7 of all the counting channels are connected to the counting input of the counter 24 and through the frequency divider 12 to the pulse generator 11, the second output of the control panel 15 is connected through the blocks 16 and 18 of the memory to the display blocks 17-20, the address inputs are multiplex Each of the counting channels 10 is connected to the output of the memory block 16, the address inputs of the multiplexer 22 and the demultiplexer 23 are connected to the output of the counter 24, the counting resolution input of which is connected to the gate inputs of the multiplexer 22 and the output of the OR 25, the output of the multiplexer 22 is connected to the first inputs of digital comparators 26 and 27, the second inputs of which are connected to the outputs of the memory block 18, and the output through the AND 28 element and directly connected to the inputs of the OR element 29, the output of which through the demultiplexer 23 is connected It is connected to the signaling devices 30, and the output of the channel selection unit 1 3 is connected to the display unit 14.

The device works as follows

For simplicity, we show the operation of one channel 1 account,

In the initial state at the direct output of the multiplexer 10 and at the second inputs of the first 3 and second 7 elements AND there is a logical one.

(i; in; iKf) I h With 41P i i. iKiiuibix imu.ch-s ov not sci 1p; n 1 imuchysy, gtstshpd iiDi him a ml approach from generator II pulses through a divider 12 h. CCG from. and the second log icha CKni i e; 1ment I 7, as it has its prohibition on its installation input - a logical unit from the inverse output three1.1. 8.

With the emergence of iiepiniro and 1I; yca from the photo sensor 2 coming through the first (1st logical element H 3 and inverter 4, the servant tinn so that the counter 5 INPUT impuhson can count only from the second pulse in order to fully calculate the first pulse The electric power meter disk trigger 8, tilting 1.1 s1., prepares the counter 5 input1.1x pulses to the account by applying to the installation disk ei o 20 revolutions of the disk drive electronic input logical zero and gives the resolution to the counter 6 clock pulses,

To automatically stop the INPUT 11X 5 and clock pulses of 6 pulses, when the 5 input pulses reach the required number of readings of the disk speed of the electricity meters, multiplexer 10 serves.

Dp matching B1) of the input of the counter 5 input pulses with the information input of the multi-detector 10 between them decoder 9. When the input counter 5 of the pulses reaches the required number of readings of the disk of the electricity counter specified by multiplexer 10 according to its input

The first bus 4ifcno data of the first memory block 16 is addressed to the address input, a logical zero appears at the forward output of the multiplexer 10, which causes the counters 5 and 6 of the input and clock pulses to stop. Thus, at the end of the counting counter 6 clock pulses at its output retains the information received,

The work of the other channels) account is similar.

To read the received information from the required account channel 1 to the first block 14 of the indicadia, the block 13 is selected for the account channels.

The verifier, via the control panel 15, on its second bus, connected to the bits of the first 16 and second 8 memory blocks, selects a certain memory cell, corresponding to rE (un111 (for the type of electric power meters and the required ry pei Jiamated mode of operation, while reading the information presented in binary 1 code from all numeric data buses of these blocks occurs simultaneously. Verifier according to the correct data,

removed from the fourth b: gok 20 of the display, sets on the test installation of the required regulated H1) operating mode of the meter electricity.

The first bus of the numerical data of the first memory block 16 associated with the address input of the multiplexer 10 informs the verifier, with the help of a second porq of the display block 17, about the amount of energy that the device counts.

The second memory block 18 sets the first and second numerical data buses,

respectively, the first and second digital comparators 26 and 27, through their inputs X, the lower X, and the upper X, the limits of the permissible error of the electric power meters being turned, and parallel to this information goes to the third display unit 19. When on all channels 1 of the counter reaches 5 input pulses, the required number of turns of revolutions

the disk of electricity meters on the first outputs of the multiplexers 10 of each channel I of the account and, respectively, on all inputs and output of the first element OR 25 there are logical zeros. The logical zero level at the output of the first log element OR 25 converts the multiplexer 22 and demultiplexer 23 from the third high-impedance state 4 (and into normal operation, and also allows the counter 24 to operate, matching the information inputs of the multiplexer 22 with the information outputs of the demultiplexer 23.

At the input of the counter 24, the arrival of t pulses from the generator I1 of pulses through the divider 12 frequency.

When a binary code synchronizing pulse 24 is set at the output corresponding to digit I, multiplexer 22 connects its output to its output of the counter of 6 clock pulses of the first channel

1 bills, and the demultiplexer 23 connects its information input to the first signaling device 1. There are 30 states of the meter being turned on,

If the value of Y of the counter of 6 clock pulses is found within the limits of the minlochss from the output of the second logical element OR 29 and correspondingly. Actually, at the first output of the demultiplexer 23 there is a level of a logical unit, which enables the first signaling device 30 of the state of the electric power meter to be turned on. If Y Y, then at the first output of a de gillish 23, there is a logic zero level,

When 24 binary synchronization pulses appear at the output of the binary counter, corresponding to figure 2, the block 21 simultaneously monitors the admissible error BCfx of the electric power meters being calibrated and performs the verification on the second counting channel, similarly to the calibration on the first counting channel. The verification of the remaining channels of the account is identical,

The use of simultaneous block

monitoring the permissible error of all calibrated electricity meters allows a significant reduction in the size of the device. In addition, device consumption of electricity is reduced.

Claims (1)

Invention Formula A device for automatic calibration of electricity meters, comprising a pulse generator, the output of which is connected to a frequency divider, a channel selection unit, an output which is connected to the first display unit, the control panel, the first output of which is connected to the channel selection unit, the second output to the inputs of the first and second memory blocks, the outputs of the first memory block are connected to the second and third display blocks, two outputs of the second memory block are connected to the inputs of the fourth display unit, respectively. multigiksor, counter, n alarm 0 five 0 . 0 five tors and n counting channels, to which I wait from (5 holds a sender, whose output is connected through serially connected first element AND and an inverter to the counting input of an input pulse counter, whose output through a decoder and multiplexer of the channel is connected to the first input the second element I, the output d of which is connected to the counting input of the clock counter, the counting input input of which is connected to the counting input enable of the counter of the input pulses and to the trigger output, the first input of which The second inputs of the flip-flops of all counting channels are connected to the third output of the control panel, the second inputs of the second elements And all the counting channels are connected to the output of the frequency divider, the outputs of the clock counters of all counting channels are respectively connected to the inputs of the channel selection unit , the address inputs of all multiplexers of all n count channels are connected to the output of the first memory block, characterized in that, for the sake of simplification, two digital comparators, the AND element, two OR elements and de an ultiplexer whose address inputs are connected to the multiplexer address inputs and to the counter output, the counting input of which is connected to the gates of the multiplexer and demultiplexer and to the output of the first OR element, whose inputs are connected to the outputs of the multiplexers of each of the counting channels, outputs clock counters of each of the n count channels are connected to the multiplexer inputs, the output of which is connected to the first inputs of digital comparators, the second inputs of which are connected to the outputs of the second block n accordingly, the first outputs of the comparators are directly, and the second outputs through the AND element are connected to the inputs of the second OR element, the output of which is through a demultiplexer connected to each of the n signaling devices, and the divider output is connected to the counter input of the counter.