RU1815664C - Device for monitoring time of equipment operation - Google Patents

Abstract

The invention relates to instrumentation, to time interval monitoring systems and can be used in automated equipment control systems. The purpose of the invention is to increase the reliability of the device. The device comprises a pulse generator 1 with an output frequency divider 11, a first counter 2, a second counter 5. a third counter 14. The outputs of the counters 2, 14, as well as the outputs of the driver 12 of the control signals and the multiplexer 15 are connected to the inputs of the memory block 4. The inputs of the galvanic isolation unit 8 are the inputs of the device and are connected to the monitored objects, and its outputs are connected through a switch 3 in series. The signal duration selector 9 and the single signal shaper 10 are connected to the counter 5. At the outputs of which On the other hand, a time interval code is generated, which, through the decoder 7, is transmitted to the indicator 20. In the comparison block 6, the information of the counter 2 and the channel code are output bitwise from the output of the channel code generator 18 and, if they are equal, a signal is output to the decoder 7, and on the indicator 20 The running time of the selected operator is displayed. At the same time, using the sensor 17, the former 18 and the decoder 19, the number of the selected channel is displayed on the indexer 21. 1 ill. Ј

Description

The invention relates to instrumentation, to time interval monitoring systems and can be used in automated equipment control systems.

The aim of the invention is to increase the reliability of the device.

The drawing shows a block diagram of a device.

The device comprises a pulse generator 1, a first counter 2, the output of which is connected to the control input of the switch 3 and to the first control input of the memory unit 4. The second counter 5 and the comparison unit 6 are connected to the inputs of the first decoder 7. The device also includes a unit 8 for galvanic isolation of the input signals, a signal duration selector 9, a single signal shaper 10, a frequency divider 11, a control signal shaper 12, a shift register 13, a third counter 14, multiplexer 15, first and second setters 16. 17, code generator 18, second decoder 19, first and second indicators 20. 21. The outputs of block 8 are connected to the information inputs of switch 3, the output of which is connected in series with a single selector 9 and driver 10 are connected to the counting input of the second counter 5, the outputs of which are connected to the information inputs of the multiplexer 15. The output of the first setter 16 is connected to the third input of the first decoder 7, the outputs of which are connected to the inputs of the first indicator 20. The first output of the generator 1 is connected to the first input of the shaper 12, the first output of which is connected to the Write-read input of block 4, the second and third outputs of the shaper 12 are connected respectively to the Gating register 13 input and the Overwrite input l of the second counter 5. The second output of the generator 1 is connected to the input of the frequency divider 11, the first output of which is connected to the second input of the driver 12 and the input of the third counter 14, the output of which is connected to the second control inputs of block 4 and to the control inputs of the multiplexer 15. output which is connected to the address input of block 4. The second output of the divider 11 is connected to the third input of the driver 12 and to the input of the first counter 2, the output of which is connected to the first input of the block 6. The first and second outputs of the second setter 17 are connected to the control the input of the second decoder 19 and the input of the former 18. the output of which is connected to the second input of the bis block by the information input of the second decoder 19. whose output is connected to the input of the second indicator 21. The inputs of block 8 are the inputs of the device, the output of block 4 is connected to the information input of the register 13, the outputs of which are connected to the information inputs of the counter 5.

The device operates as follows.

When the device is turned on for the first time (supply voltage to it), all the cells of the memory block 4, implemented on integrated circuits of the functional RAM series, enter the initial information - level O. Monitoring objects from O

5 to p (in the particular device under consideration, the number of control objects is 50) can be installed in their regular places at any time during operation. Block 8 is designed for galvanic isolation of power and control circuits with connected monitoring objects, increasing noise immunity and coordinated input signal reception. Implemented block 8 on optoelectronic keys.

5, If there is an input signal (signal of the switched on monitoring object), level 1 appears at the corresponding output of block 8, and if it is absent, level O appears. Signals from the outputs of block 8 are sent to

0 inputs of switch 3, at the control input of which a sequential enumeration of addresses from 1 to 50 takes place. Accordingly, at the output of switch 3, level 1 appears in each clock

5 included control object or level O in its absence.

The signal fed to the control inputs of switch 3 is generated in counter 2. Counter 2 is a 50-pulse binary counter controlled by a clock signal from divider 11. The signal generated at its output is a six-bit parallel binary channel number address code.

5 The duration of one cycle (T) of the channel number address code is determined by the frequency of the signal supplied to the counting input of counter 2. and depends, in general, on the number of monitored objects and the accuracy of measuring the running time of monitored objects. The device has a discrete measurement of operating time of 1 s. In each clock cycle in the third counter 14, a binary parallel code is generated with 5 bits, in general, determined by the capacity of the counter information 5. The proposed device is designed to measure the running time of controlled objects in the / range up to 10,000 hours. When recording this information in

RAM in the format of a binary decimal code will require 32 memory cells (for each of the 50 channels), and the number of bits of the counter 14, forming a binary parallel code of the memory cell address for polling the corresponding cells, should be 5.

Thus, the signals from the output of counter 2 form a code for the address of the channel number, and in each cycle at the outputs of counter 14 a code of addresses of memory cells is generated. These signals are fed to the inputs of block 4, the operation of which is controlled by the signal from the output of driver 12.

The driver 12 of the control signals generates a Write-Read (WR / RD) signal of the information of the memory unit 4. The operation algorithm of the memory unit 4 in each clock cycle is based on reading the information recorded in the previous clock cycle. increasing it by one in the lower order in the case of an on state corresponding to the given clock cycle of the number of the monitored object and overwriting the newly received information at the read address.

Information representing a thirty-two-bit sequential binary decimal code. read from memory unit 4, is recorded in shift register 13. designed to convert code to parallel view. The information thus obtained from the Overwrite signal is then rewritten to counter 5. It is a series-connected binary decimal counter that implements the count in the format of a single time system - hours, minutes, seconds. The strobe signals for the shift register 13 and the Overwrite are generated in the driver 12 implemented on the logic elements. After recording information in the counter 5 in the selector 9, the level of the signal present at its input in this cycle is analyzed.

The selector 9 is designed to increase the noise immunity and reliability of the device, based on a comparison of the levels of the true and delayed input signal and can be implemented on the delay element and the element I. In the event that the input signal after analysis is perceived as a reliable level 1 (which corresponds to the included state of the corresponding monitored object), an output signal is generated at the output of the selector 9, by which the driver 10 generates an increment signal, which is fed to the counting input m 5. adshey counter stage increasing its content

per unit. Otherwise, the increment signal is not generated and the state of the counter 5 remains unchanged (similar to the information stored in the memory unit 4 in the previous clock cycle). The information thus obtained in counter 5 is converted in the multiplexer 15 into a serial thirty-two-bit binary decimal code and is overwritten at the read address into the memory unit 4.

In a similar way, the device operates while monitoring the remaining 49 channels.

To visually control the operating time of a particular object, the operator, using a dial 17, which is, for example, a button with a chatter elimination circuit, generates a binary parallel code at the output of shaper 18 in a format similar to counter 2 code. At the same time, this signal through the decoder 19 enters the channel number indicator 21, where the values of the selected channel are displayed in decimal form. If the current value of the code from the outputs of counter 2 is bitwise and the static value of the code from the outputs of channel code generator 18 at the output of comparison unit 6, an enable signal is generated to write information of the counter 5 in this clock to decoder 7, and the run time value of the selected one is displayed on indicator 20 the operator of the object in the presence of a permission signal from the setter 16.

The switch 16 is made similar to the sensor 17.

The device operates in the presence of primary voltage, while all functional units are provided with a stabilized voltage from the secondary power supply unit (not shown in the drawing). In order to save operational information during emergency or routine power off, a backup power supply implemented on batteries or accumulators can be introduced into the device and providing power to the memory elements of unit 4. "

Thus, the introduction of new elements and blocks makes it possible to reliably determine the operating time of the controlled equipment, to quickly evaluate information about the operating time of objects and make the necessary decisions, while the device reliably functions in real operating conditions and interference conditions, storing time information operating time during power failure or disconnection.

Claims (1)

The claims A device for monitoring the operating time of the equipment, comprising a pulse generator, a first counter, the output of which is connected to the control input of the switch and the first control input of the memory unit, a second counter and a comparison unit, the output of which is connected to the first input of the first decoder, characterized in that , in order to increase the reliability of the device, a block of galvanic isolation of the input signals, a signal duration selector, are introduced into it; single signal shaper, frequency divider, control signal shaper, shift register, third counter, multiplexer, first and second setters, code shaper, second decoder, first and second indicators, outputs of the galvanic isolation unit are connected to the information inputs of the switch the output of which is connected through a series-connected selector of the signal duration and the shaper of single signals to the counting input of the second counter, the outputs of which are connected to the information inputs of the mul the typlexer and the second inputs of the first decoder, the third input of which is connected to the output of the first master, and the outputs of the first decoder are connected to the inputs of the first indicator, the first output of the pulse generator is connected to the first input of the driver of the control signals, the first output of which is connected to the Write-read memory input The second and third outputs of the driver of the control signals are connected respectively to the input Gating the shift register and the input Overwriting the second counter, the second output of the pulse generator c is connected to the input of the frequency divider, the first output of which is connected to the second input of the driver of the control signals and the input of the third counter, the output of which is connected to the second control inputs of the memory unit and the control inputs of the multiplexer, the output of which is connected to the address input of the memory unit, the second output of the frequency divider is connected to the third input of the driver of the control signals and the input of the first counter, the output of which is connected to the first input of the comparison unit, the first and second outputs of the second setter are connected to the control input of the second decoder and the input of the code generator, the output of which is connected to the second input of the comparison unit and the information input of the second decoder, the output of which is connected to the input of the second indicator, the inputs of the galvanic isolation unit are the inputs of the device, the output of the memory unit is connected to the information input shift register, the outputs of which are connected to the information inputs of the second counter.