RU2024968C1 - Device for diagnostic inspection of playback channel of digital magnetic recording equipment - Google Patents

Abstract

FIELD: magnetic recording. SUBSTANCE: device has commutator unit 1, two former units 2, two units for measuring time intervals, two registrar units 4, read-out unit 5, number selecting unit 6, synchronization unit 7, rejection pulse forming unit 8, control inputs 13-16 of the device; the inputs are connected with system control unit and with processing unit, for example, microcomputer. EFFECT: improved precision of checking. 12 dwg

Description

 The invention relates to techniques for magnetic recording and can be used with instrumentation, as well as in built-in diagnostic tools for digital magnetic recording equipment (ACMZ).

 The device is intended for a qualitative assessment of the health of the ACMZ channel.

 A device for measuring fluctuations in the speed of movement of a magnetic recording medium, comprising a reproducing magnetic head, a playback amplifier, a shaper, a spectrum analyzer, a recorder, a comparator, a single vibrator and a mismatch element connected in series, a two-channel converter of the pulse duration into voltage and a combining element [1].

 However, the device does not have a sufficiently high measurement accuracy; its electrical circuit is complex and energy-consuming, moreover, it has narrow functional capabilities (there is no control of the reproduced signals of the ACMZ).

 Also known is a device for controlling the synchronism of reproduced signals, comprising a pseudo-random signal bus, a first adder, a pseudo-random sequence detector, a no-error detector, a switch, a second adder, a first shift register, a trigger, an output bus, a clock bus, an additional shift register, a code generator, a memory register, clock failure generators, each of which consists of a series-connected adder, a clock counter and a trigger, the device also contains output bus signals of mismatch and OR elements [2].

The main disadvantage of the device is its narrow functionality (it measures only the magnitude of the signal mismatch, monitors the synchronism, but does not "identify" the source of disturbances of the mismatched signals), i.e. does not allow to qualitatively evaluate the performance of the ATSMZ
.

 The closest in technical essence and the achieved effect to the proposed device is a device for measuring the magnitude of the mismatch of the playback signals from the magnetic tape, containing a series-connected block of magnetic heads and a playback amplifier, series-connected the first counter and the documentation unit, the second counter, the input of which is connected to the input of the first counter, in addition, the device contains a series-connected encoder, switch, block forming normalized them pulse, the circuit for measuring the measured pulse, the circuit for generating the reset pulse and the reading unit, the unit for measuring time intervals, the outputs of which are connected to the second inputs of the switch and the reading unit, the output of which is connected to the input of the first counter, and the third input is connected to the second output of the circuit for measuring the measured pulse the third output of which is connected to the input of the time interval measuring unit, the second output of the encoder connected to the input of the magnetic heads unit, the third input of the switch is connected to the amplifier output a playback amplifier, and the second input of the circuit for measuring the measured pulse is connected to the output of the switch [3].

 The disadvantage of this device is the narrow functionality (insufficient accuracy and information content of the control, which does not allow a qualitative assessment - to analyze the operability of the monitored device) measures only the amount of mismatch and only one type of monitored signals is subject to monitoring.

 The aim of the invention is to increase the accuracy and information content of control over independent channels relative to the service control signal.

 This goal is achieved by the fact that the device for measuring the magnitude of the mismatch of signals from the magnetic tape containing the switch unit, the first driver unit, the first unit for measuring time intervals, the reader unit, the unit for generating a reset pulse, the output of which is connected to the reset input of the reader unit, the first the input of the mode selection of the switch unit is the control input of the device, the first information input is the information input of the device, and the first output is the information input of the device about the block-shaper, the first block of registration, introduced the second block of shapers, the second block of measurement of time intervals, the second block of registration, block number selection, synchronization block, block number selection, synchronization block, block system control and processing of microcomputers, and the second and third input block mode selection, the first input of the mode selection of the number selection block, the reset input of the reset pulse forming unit, the mode selection input of the first and second block of the driver, the clock input of the registration unit of the first and W The channel, the clock input of the reader is a group of device control inputs for connecting to the corresponding micro-computer control outputs, and the information output of the reader is the output of the device activity indicator for connecting to the micro-computer activity confirmation input, the first, second and third information input the switch unit are respectively the service and information inputs of the device for connecting to the control and monitored inputs of the monitored device, and groups inputs of the switch block number attribute is connected to the group of outputs of the number selection block, the first reset input of which is connected to the input of the reading block, with the first reset input of the switch block, with the reset input of the first and second block of formers, the first and second registration block, and the second input of mode selection the number selection unit is connected to the third output of the mode selection of the switch unit, to the first input of the mode selection of the synchronization unit, the first clock input of the number selection unit is connected to the first output of the synchronization unit and to the clock input of the first and second shaper, the third input of the mode selection of the number selection unit is connected to the second output of the switch unit and to the input of the mode selection of the synchronization unit, the second and third output of which is connected to the clock input of the first and second time interval measurement unit, respectively, and the fourth and the fifth output is a group of control outputs of the device, and the third output of the switch unit is the second clock input of the number selection unit, the second input of the reset flag of which is connected to the first output of the switch block, the fifth output of which is the information input of the second block of the driver, and the sixth and seventh outputs of which are connected to the input of the first and second block of the drivers, the first output of which is connected to the input of the sign of loading, respectively, of the first and second block of measurement of time intervals, a group of outputs which is an information group of inputs of the first and second registration unit, respectively, the output of the sign of filling the buffer of which is connected to the input sign respectively, of the first and second block of the driver and to the group of inputs of the sign of filling the buffer of the first and second channels of the reading unit, the output of the sign of filling the buffer of two channels of which is the second reset input of the switch unit, the first and second group of information inputs of the reading unit are connected to the groups of outputs of the registration unit, input recording features which are connected to the second input, respectively, of the first and second block of formers, the input of the transfer attribute of which is the output, respectively, of the first and a second measurement unit time slots, which control input is the third output of the first and second generators. The switch unit contains the first to fifth element NOT, the first to fourth element 2-2 AND-OR-NOT, the first and second one-shot, the first to eighth element 2 AND, element 2 AND-NOT, the first-third element 2 OR-NOT, the first- fourth element 2 OR. The first and second block of the driver includes a first to third one-shot, D-flip-flop, element 2 OR, element 4I, element 2I-NOT, element NOT, resistor and capacitor (delay element). The first and second time interval measurement unit comprises a counter and a bus driver. The registration unit contains an IK trigger, counter, RAM element, the first and second element 2 AND, 2 OR, and the element NOT. The reading unit contains a multiplexer, a first and a second counter, a decoder, an OR element, and NOT. The number selection block contains the first and second counter, the first and second IK trigger, the first and second element 2 AND, element 2I-NOT and NOT, a block of resistors, indicators, switches. The synchronization unit contains a counter, element 2 AND-OR-NOT, element 2I, a clock generator. The reset pulse generating unit comprises a 2I-NOT element, a resistor and a capacitor. The input of the first element is NOT and the first input of the third element 2I is the switch unit, the input of the second element is NOT and the third input of the first element 2-2I-OR-NOT, the input of the third element is NOT and the third input of the second element 2-2I-OR-NOT which are the first third the input of the mode selection of the switch unit, the input of the fourth element is NOT and the fourth input of the first element 2-2I-OR-NOT, the first input of which, the first input of the first element 2I are, respectively, the first or third control input of the switch unit, the first input of the second element 2 OR-NOT, second input of the first element 2I, the first input of the third element 2, OR NOT is respectively the first or third information input of the switch unit, and the first input of the fourth element 2I is the first reset input of the switch unit to connect to the output of the element 2I-NOT the block for generating the reset pulse, to the reset input of the first IK -trigger, to the input input of the first and n-input of the first counter of the number selection unit, to the first input of the first element 2I, to the reset input of the first one-shot and to the first input of element 4I of the first and second block of the driver, to the reset input of the IK trigger of the first input of the second element 2and the reset input of the first and second registration unit, to the input of the second element of the reader unit, the reset input of the first and second one-shot of the switch unit is the second reset input of the switch unit to connect to the output of the first element of the reader unit , the first input of the second element 2I and the second input of the third element 2I, the first input of the sixth element 2I, the first input of the first element 2 OR NOT and the fourth element 2 OR are a group of inputs a mutator for connecting, respectively, to the output of the second IK trigger, which is connected to the first input of the 2I-NOT element, to the output of the second IK-trigger, and to the inverse output of the second IK trigger, which is connected to the input to decrease the second counter of the number selection block, and, the output the first element NOT of the switch unit is connected to the second input of the second element 2I, the sixth element 2I, to the first input of the fifth element 2I and is the second output of the unit for connecting to the first input of the second element 2I of the number selection unit and to the first input element 2-2I-OR-NOT synchronization unit, and the output of the second element NOT switching unit is the second input of the first element 2-2I-OR-NOT, and the output of the third element NOT switching unit is the second input of the first element 2 2AND-OR-NOT, and the output of the third element is NOT connected to the first input of the second 2-2I-OR-NOT element, the outputs of which are connected to the first and second inverse input of the first and second one-shots, the second inverse and first input of which is connected to the bus of zero and unit potential, and accordingly to the entrance of the fifth eleme that NOT, the output of which is the third output of the block for connecting to the clock input to increase the second counter of the number selection block, and the output of the fourth element of the NOT block of the switch is the second input of the elements 2 OR NOT 2 OR, the outputs of which are connected to the second input of the second and third element 2 OR NOT and the first input of the seventh and eighth element 2I and, respectively, with the second input of the fifth element 2I, the output of which is the first input of the first OR element, the output of which is the sixth output of the switch unit, and the output One of the fourth ORI element 2 is the seventh output of the switch unit for connecting to the second input of the 4I element the first and second block of drivers, respectively, and the outputs of the first and second single-vibrator of the switch unit are connected to the second input of the second element 2-2I-OR-NOT and, respectively, with the first input of the element 2I-NOT, the second input of which is the output of the second element 2I, and the output of which is the second input of the fourth element 2I, the output of which is the fourth output of the switch unit for connecting to the reset input of the second IK-trigger of the mode selection unit, and the output of the first element 2I of the switch unit is connected to the fourth input of the second element 2-2I-OR-NOT, to the second input of the seventh and eighth element 2I and to the first input of the third element 2-2I-OR -NOT, the second input of which is connected to the output of the third element 2I and connected to the second input of the first element 2 OR and to the second input of the fourth element 2-2I-OR-NOT, the third input of the third element 2-2I-OR-NOT connected to the output of the sixth element 2I and with the third input of the fourth element 2-2I-OR-N the first and fourth inputs of which and the fourth input of the third element 2-2I-OR-NOT are respectively the outputs of the third and second elements 2OR, the first outputs of which are connected respectively to the outputs of the third and second elements 2OR-NOT, and the second inputs of which are connected respectively to the outputs the eighth and seventh element 2I, and the outputs of the third and fourth element 2-2I-OR-NOT, are the first and fifth output of the switch unit for connecting to the second inverse and first input of the first and second one-shots, respectively about the first and second block of the shapers, the first and second inverse inputs of the first and second single vibrators connected to the unit and zero potential buses, and the outputs connected to the first and second input of the 2OR element, the output of which is the first input of the 2AND-NOT element and the data input D- a trigger, the clock input of which is the clock input of the first and second block of drivers for connecting to the first output of the counter of the synchronization block and which is connected to the second input of the element 2 AND NOT block number selection, and the third The data output of the D-flip-flop of the first and second block of drivers is connected to the first input of the third one-shot, the second inverse input of which is connected to the zero potential, and the third inverse data output of the D-flip-flop is the second input of the 2AND-NOT element, the output of which is connected to the input of the NOT element and is the third output of the first and second block of drivers for connecting to the input at the control attribute of the bus driver, respectively, of the first and second block for measuring time intervals, and the output of the third one-shot The first and second block drivers are connected to the first contact of the resistor and capacitor and to the clock input of the IK trigger, and the inverse output of the third one-shot is connected to the third input of the 4I element, the output of which is connected to the first input of the second 2I element, the output of which is the reset input IK- a trigger, the first and second information input of which and the second contact of the resistor and capacitor are connected respectively to the unit and zero potential, and the output of the IK trigger is the first output of the first and second block of pho leaders to connect to the input of the sign of loading the counter of the first and second block of measurement of time intervals, moreover, the output of the element NOT of the first and second block of formers is the second input of the block for connecting to the first input of the sign of recording the first element 2I and the first and second registration unit, the second input of the element 2I is connected to the inverse output of the IK trigger, which is the output of the first and second registration unit for connecting to the fourth input of element 4I, respectively, of the first and second block of the form to the first and second input of the 2OR-NOT element, the first input of the OR element of the first and second registration unit being the clock input of the block, the second input of the element NOT connected to the output of the first 2I-NOT element, and the output to the input of the NOT element, the output of which connected to the clock input of the counter and to the first input of the second OR element 2, the output of which is the input of the sign - write - read RAM element, and the second input of which is connected to the output of the IK trigger, the K input of which is connected to the unit potential, whose clock input is is connected with the output of the counter transfer indicator and connected to the second input of the second element 2I, the output of which is connected to the download input at the input of the code combination of the counter, the output group of which is a group of address inputs of the RAM element, the output group of which is a group of outputs and a group of information inputs, respectively, of the first and a second registration unit for connecting to the inputs of the multiplexer of the reading unit and, accordingly, to the output of the bus driver of the first and second time measuring unit of intervals, the group of inputs of which is connected to the group of outputs of the counter, the group of data inputs of which is connected to zero potential, and the output of the 2-NAND element of the reader unit is connected to the input of the NAND element and to the first input of the multiplexer, the group of outputs of which is the information output of the read unit, and the first and second group of the control attribute of which is a group of outputs of the first counter and decoder, respectively, the first inverse and second control input of which is connected to the third output of the second a counter, and the second inverse and first input of which are connected to the bus of zero potential, the first and second outputs of the counter connected to the first and second information inputs of the decoder, the clock input of which is connected to the second output of the first counter, the clock input of which is the information output of the reader, input the data of which is a certain code combination, and the reset input of the second counter is the output of the second element NOT, and the output of the generator of the synchronization unit is connected to the clock the output of the counter, with the first contact of the switch, with the second input of the 2-2I-OR-NOT element and is the second output of the block, and the output of the second 2-2I-OR-NOT element is the third output of the block for connecting to the clock input of the counter, respectively, the second and of the first time interval measuring unit, the third input of the 2-2I-OR-NOT element is connected to the first input of the mode selection of the switch unit, and the fourth input is connected to the output of the 2I element, the first input of which is connected to the second contact of the switch, the second input of which is connected to a contact of the switch, the fourth contact of which is connected to the first output of the counter, the second and third outputs of which are a group of control points of the synchronization unit, the second contacts of the push buttons of the number selection unit are connected to zero potential, and the second to the clock inputs, respectively, to decrease the first counter, the groups of outputs of which are the groups of the first contacts of the resistor block and the groups of data inputs of the second counter, the input of the loading sign of which is connected to the first input of the first element 2I and with the output of the element NOT, the input of which is the first input of the mode selection of the number selection block, the output of the transfer flag of the second counter of which is the second input of the 2I element, the output of which is connected to the clock input of the second IK trigger, and the clock input of the first IK trigger connected to the output of the 2I-NOT element, with the inputs K of the first and second IK triggers connected to the zero potential, and the output of the first connected to the second input of the second element 2I, and the group of second contacts of the resistor block is connected to the group of of the first contacts of the indicators, the group of second contacts is connected to the unit potential, the first input of the 2I-NOT element of the reset pulse forming unit is the reset input of the unit, and the second input is connected to the first contact of the resistor and capacitor, the second contacts of which are connected to the unit and zero potential, respectively.

 Figure 1 presents the structural diagram of a device for diagnostic control of the playback channel ACMZ; figure 2 is a block diagram of a switch; in FIG. 3 is a diagram of a first and second block of formers; figure 4 - diagram of the first and second unit of measurement of time intervals; figure 5 - diagram of the first and second block of the registrar; 6 is an account diagram of a reading unit; 7 is a diagram of a block for selecting a number; on Fig is a block diagram of a synchronization; figure 9 is a diagram of the formation of a reset pulse; figure 10 - algorithm for the joint operation of the device with a microcomputer and with a controlled device; in FIG. 11 is a timing diagram of the operation of the device; 12 is a fragment of a printout of statistical analysis on two independent channels.

 The diagnostic monitoring device of the reproduction channel of the ACMZ (see Fig. 1) contains a switch unit 1, a first and a second unit of formers 2, a first and a second unit 3 for measuring time intervals, a first and a second unit 4 of a recorder, a reading unit 5, a number selection unit 6, block 7 synchronization, block 8 forming a reset pulse and has a first 9, second 10 and third 11 input mode selection block 1, input 12 reset block 8, input 13 mode selection of the first and second block 2, the first input 14 mode selection block 6, clock input 15 of the first and second block 4, clock the input 16 of block 5, which are the control inputs 13-16 of the device for connecting to the corresponding control outputs of the micro-computer, and the information output 17 of block 5, which is the output of the sign of activity of the information of the device, is connected to the input of the confirmation of the sign of the micro-computer, the first 18, the second 19, third 20 control input and the first 21, second 22, third 23 information inputs of block 1, which are respectively service inputs 18-20 and information inputs 21-23 of the device, are connected to the control and monitoring outputs of the con a rooted device, moreover, the group of inputs of feature number 24 of block 1 is connected to the group of outputs of block 6, the first reset input 25 of which is connected to the reset input of block 5, with the first reset input of block 1, with the reset input of the first and second blocks 2 and 4, and the output of block 8. The first clock input 26 of block 6 is connected to the first output of block 7 and to the clock input of the first and second block 2, the second input 27 of the mode selection block 6 is connected to the second output of block 1, and with the second input of the choice of mode block 7 second 28 and the third 29 outputs of which are connected to the clock the first and second block 3, respectively, the fourth and fifth output of which are the group 30 of the control outputs of the device, the third output of block 1 is the second clock input 31 of block 6, the second input 32 of the reset flag of which is connected to the fourth output of block 1, the first and fifth outputs of which are respectively the information inputs 33 of the first and second blocks 2, and the sixth and seventh outputs of which are connected to the inputs 34 of the first and second blocks 2, respectively, the first output of which is connected to the input 35 of the sign of loading with respectively, of the first second block 3, the group of outputs of which is an information group of inputs 36 of the first and second block 4, the outputs of the buffer filling flag 37 of which are connected to the characteristic input of the first and second block 2, and to the group of inputs of the buffer filling indicator of the first and second channels of block 5, the output of the buffer fill indicator of the two channels of which is the second input 38 of the reset block 1, the first and second group of information inputs of the block 5 is connected to the output groups 39 of the blocks 4, the input of the recording characteristic of which is connected ene to a second output 40 of the first and the second unit 2, which is a transfer characteristic input 41 output respectively the first and the second unit 3, the control input 42 which is the third output of the first and the second unit 2.

 The switch unit 1 (see FIG. 2) contains an element NOT 43, an element 2 2-NOR 44, a single vibrator 45, an element 2 I 46, an element 2 NAND 47, an element 2 OR NOT 48, an element 2 OR 49.

 The driver unit 2 (see FIG. 3) contains a single vibrator 50, D-trigger 51, IK-trigger 52, element 2I 53, 2OR 54, element 4I 55, element 2I-NOT 56, element NOT 57, delay element 58, consisting from resistor and capacitor.

 The unit for measuring time intervals 3 (see figure 4) contains an OR element 59, a counter 60, a bus driver 61.

 The registration unit 4 (see Fig. 5) contains an IK trigger 62, a counter 63, an element of RAM 64, an element 2 AND 65, an element 2 OR 66, an element NOT 67.

 The reading unit 5 (see Fig. 6) contains a multiplexer 68, a counter 69 and 70, a decoder 71, an OR element 72, an element NOT 73.

 The number selection block 6 (see Fig. 7) contains a counter 74 and 75, an IK trigger 76, an element 2I 77, an element 2I-NOT 78, an element NOT 79, a block of resistors 80, indicators 81, push-button switches 82.

 The synchronization unit 7 (see Fig. 8) contains a counter 83, an element 2I-OR-NOT 84, an element 2I 85, a clock generator 86; switch 87.

 Block reset pulse 8 (see Fig.9) contains a 2I-NOT 88 element, resistor 89, capacitor 90.

 The switch unit 1 is designed to select one of the combinations of modes received by the first or third input 9-11 of the mode selection (SIZE, TAC, BLOCK NUMBERS, FILE) from the microcomputer in accordance with the algorithm (Fig. 10), for setting control by signs (BLOCK, MARKER, FILE, MOVEMENT), on the first or third input 18-20 of the control unit for the purpose of switching signals (TAC, PLAYBACK DATA WITH ML and SYNCHRO) generated in the controlled device (in the playback channel ACMZ) and received on the first third 21-23 information inputs of the block and further to the first and second 2 nd block formers.

 The first and second block 2 of the normalized pulse generator is designed to generate control signals from the first 35, third 42 and second 40 outputs of the block, respectively, to the input of the sign of loading and control of the first and second block 3 of measuring time intervals, and to the input of the sign of recording the first and second block 4 registration in accordance with the time chart (see Fig.11).

 The first and second block 3 measurement of time intervals is designed to calculate the period of repetition of pulses of information signals received from the monitored device through independent channels 33 from the first and second blocks 3 relative to the service signal 34 and 13, generated under the control signals of the ACMZ and microcomputer in accordance with the algorithm (see figure 10).

 The first and second recording unit 4 is designed to store an information array formed from the measured time intervals of the monitored signals coming from the first and second blocks 3 via independent channels 36 in recording mode at the moments determined by the signals from the output 40 of the first and second block 2 of the shapers in accordance with the time chart (see Fig.11).

 The reading unit 5 is intended for reading the information array entered in the write mode in the RAM 64 of the first and second unit 4 into the microcomputer, under its control through the output 17 of the unit in the reading mode after the sign of buffer filling is formed.

 The number selection unit 6 is used to select a feature number (from which unit, file or TAC number to start the recording process) using the push-buttons 82, followed by its application in the reverse code through the counter 74 and into the counter 75 with the simultaneous display of the number on the indicators 81, to find the number in the process of operation of the controlled device under the control of the micro-computer, as well as to form a group of 24 signals of the sign of the number received in block 1 of the switch.

 Block 7 synchronization is designed to generate clock signals received from the outputs 28 and 29, respectively, to the clock input of the first and second block of measurement of time intervals, as well as to generate textured signals, representing a control group 30 of the block. The choice of a feature of the mode (playback or TAC) is carried out using the switch 87.

 Block 8 of the formation of the reset pulse is designed to generate a signal for the initial installation of the device in the initial state and reset under the control of the microcomputer through the reset input in accordance with the algorithm (see Fig. 10).

 It is proposed to use the 155АГЗ microchip as a single-vibrator 50 of the shaper unit 2, and the 531ТМ8 D-flip-flop.

 As the counter 60 of block 3 can be used chip 531IE17.

 The RAM 64 of the first and second registration unit 4 is a static type RAM (for example, 1K4X10 capacity) 132RU8, and a chip 555IE7 (four-bit asynchronous counter) can be used as counter 63.

 The multiplexer 68 of the reading unit 5 is a 555KP12 chip, and the counters 69 and 70 can be 555IE7 and IE5 chips.

 The 555IE7 chip can be used as a counter 74 and 75 of the number selection unit 6, and LEDs of the ZLS341B type can be used as indicators.

 As a counter 83 of synchronization unit 7, a 531IE17 type microcircuit can be used, and as a generator, any crystal oscillator compatible with TTL or a Pierce crystal oscillator using a field effect transistor with a frequency of generation up to 50 MHz (Electronic circuits, 1300 examples, edited by R. Count, Moscow "Mir", 1989).

 The device operates as follows.

 To bring the diagnostic control device of the playback channel ACMZ to its initial state, the first reset input of block 1, the reset input of the first and second blocks 2 and 4, 5, and the first reset input of block 6 receive the signal "Reset + Initial setting" from output 25 of block 8 , which is formed after turning on the power or under the control of a microcomputer from output 12 in accordance with the algorithm (see figure 10).

 As a result, the one-shots 50 of the first and second block 2, IK-flip-flops 62 of the first and second block 4, the counter 70 and the IK-flip-flop 76.1 of block 6 are set to the initial state, the "Write permission" signal is generated at the outputs of the IK-flip-62 in RAM 64, permission to the account through the elements 65.1, 66.1 and 67 of the counter 63, and the absence signal "Buffer full", which through the elements 55 and 53.2, and the reset input of the IK trigger 52 of the first and second blocks 2 prohibits the counting of the counter 60 of the first and second blocks 3 and translates it into a boot state with a null code combination. In addition, at the output of the IK-trigger 76.1 of block 6, the level of absence of a number indicator is set, which prohibits the passage of information from the monitored device through independent channels through the elements 44.3 and 44.4 of block 1.

The device operates in two modes:
- in recording mode, the monitored information from the monitored device in real time passes through the elements 44.3 and 44.4 of block 1 through two independent channels to the first and second block 2, respectively, to generate normalized pulses 40 and 43 and 35. Using signal 35, which is input If the counter 60 of the first and second blocks 3 is loaded, the measured pulse is counted by the clock pulses generated from the outputs 28 and 29 of the synchronization block 7, and this signal is recorded using signals 40 and 42 ranks through the bus driver 61 in the OP 64 of the first and second unit 4 at the appropriate address:
- in the mode of reading information from RAM 64 of the first and second blocks 4 is read simultaneously from two channels through the multiplexer 68 of block 5 in the microcomputer to input 17, under its control on lines 15 and 16.

 The separation of these modes in time is solved by the device equipment and the control of the microcomputer in accordance with the algorithm (see Fig. 10).

 The device is multifunctional and allows you to create information arrays relative to the service signal with subsequent statistical analysis in micro-computers. The following signs from the monitored device can be used as a service signal: “Block”, “File marker”, TAC together with the “Motion” signal. Depending on the control combination of mode selection on lines 9-11 from the microcomputer, the information array can be entered in the OP 64 with respect to any TAX number, block, file marker. The device has the following main functions: determination of oscillations to the speed of MN; in playback mode (determination of phase and frequency shifts when the synchronization systems of the ACMZ enter synchronism and check its operability in the process of tracking reproducible information, followed by statistical analysis; determining the nature of reproducible information read from any two MN tracks via independent channels); resolution of a conflict situation in the event of failure of individual nodes of the ATsMZ (path of moving the MP or the reproduction channel of the ATsMZ). Identification of the source of disturbance is carried out in the mode of determining fluctuations in the velocity of MN in the path of its movement by statistical analysis of the values of the measured pulses received from the controlled device along lines 21, 23, the sign "Information signal" and 22 sign - "TAC".

 The control device for the diagnostic control of the playback channel is carried out by the control outputs 9-16 of the micro-computer in accordance with the algorithm (see figure 10).

 The recording mode of information received from the control outputs 21-24 of the monitored device occurs according to the time diagram (see Fig. 11), and the mode of reading information from RAM 64 to the microcomputer by output 17 in accordance with the algorithm of Fig. 10.

с выходов 9-16 микро-ЭВМ (фиг.10а). Для блокировки сигнала 16 "Буфер 16 заполнен" на вых. 17, а также для приведения устройства в исходное состояние по выходу 12 формируется сигнал "Сброс буфер заполнен" который, поступая через элемент 2И 88 фиг.8 блока 8 сбрасывает IK-триггеры 62 по входу 25 первого и второго блока 4 фиг.5. В результате на 17 выходе через элемент 2ИЛИ 72 и в первый вход мультиплексора 68 блока 5 считывания формируется признак отсутствия заполнения буфера и установка блоков 2, 4, 5, 6 в исходное состояние в соответствии с фиг.106 (последовательная передача кодовой комбинации с выходов 9-16 1

0

. Далее оператор через микро-ЭВМ осуществляет выбор функционального режима (определения скорости фиг.10 вг или воспроизведения - фиг.10вд). В случае определения скорости по вых. 9-16 передается кодовая комбинация (4

фиг. 10м. Затем оператором через микро-ЭВМ задается дополнительная информация в зависимости от функционального режима (см. фиг.10 г-н или фиг.10 дл). С помощью кнопочных переключателей 82 выбирается номер признака (блок, ТАХ, маркер файла) относительно которого начинается процесс формирования информационного массива по двум независимым каналам из величин измеряемых интервалов контролируемых сигналов. Т. е. оператор, последовательным нажатием кнопок 82 блока 6 фиг. 7 устанавливает номер признака в обратном коде в счетчике 74.1-74. п, который заносится по информационным входам в счетчик 75.1-75.п и там запоминается до формирования сигнала "Счет" под управлением микро-ЭВМ (фиг.14) в соответствии с алгоритмом (фиг.10р). Номер признака с выхода счетчика 74.1-74.в отображается на индикаторах 81 через резисторную сборку 80 блока 6 фиг.7. Кроме того, в исходном состоянии на выходах IK-триггеров 76.1 и 76.2 отсутствует признак "Номер найден" (группа признаков 24 блока 6 фиг. 7), который осуществляет блокировку контрольных сигналов, поступаемых с выходов 21-23 через элементы 2И 46.1 и элементы 2ИЛИ 46.2, 48.3 на первый, четвертый вход элемента 2-2И-ИЛИ-НЕ 44.3 и 44.4 блока 1 коммутатора фиг.2 устанавливает в состояние сброса через второй вход элемента 4И 55 и первый вход элемента 2И 53.2 IK-триггера 52 первого и второго блока 2. Выходы IK-триггеров в свою очередь переводят счетчик 60 первого и второго блоков 3 фиг.4 в состояние загрузки нулевой кодовой комбинации по информационному входу.The software installation of the diagnostic control device is carried out by transmitting all zeros - (0

from the outputs of 9-16 micro-computers (figa). To block signal 16 "Buffer 16 full" at the output. 17, as well as to bring the device to its initial state, output 12 generates a "Reset Buffer Full" signal which, passing through element 2I 88 of Fig. 8 of block 8, resets IK triggers 62 at input 25 of the first and second block 4 of Fig. 5. As a result, at the 17th output through the element 2 OR 72 and at the first input of the multiplexer 68 of the reading unit 5, a sign of the lack of buffer filling and the setting of the blocks 2, 4, 5, 6 to the initial state in accordance with Fig. 106 (serial transmission of the code combination from the outputs 9 -16 1

0

. Next, the operator through the micro-computer performs the selection of the functional mode (determine the speed of Fig.10 vg or playback - Fig.10vd). In the case of determining the speed output. 9-16 code combination is transmitted (4

FIG. 10m Then the operator through the micro-computer sets additional information depending on the functional mode (see figure 10 Mr. or figure 10 dl). Using the push-button switches 82, a feature number is selected (block, TAC, file marker) with respect to which the process of forming an information array begins via two independent channels from the values of the measured intervals of the monitored signals. That is, the operator, by successive pressing of the buttons 82 of the block 6 of FIG. 7 sets the feature number in the reverse code at counter 74.1-74. n, which is entered at the information inputs into the counter 75.1-75.p and is stored there until the signal “Account” is generated under the control of the microcomputer (Fig. 14) in accordance with the algorithm (Fig. 10p). The sign number from the output of the counter 74.1-74.v is displayed on the indicators 81 through the resistor assembly 80 of the block 6 of Fig.7. In addition, in the initial state at the outputs of IK-triggers 76.1 and 76.2 there is no sign “Number found” (group of signs 24 of block 6 of Fig. 7), which blocks control signals received from outputs 21-23 through elements 2 AND 46.1 and elements 2 OR 46.2, 48.3 to the first, fourth input of element 2-2I-OR-NOT 44.3 and 44.4 of block 1 of the switch of FIG. 2 sets into a reset state through the second input of element 4I 55 and the first input of element 2I 53.2 of IK trigger 52 of the first and second block 2 The outputs of the IK-triggers, in turn, translate the counter 60 of the first and second blocks 3 of figure 4 to the boot state of the zero code combination at the information input.

 After the formation of the microcomputer by output 14 of the “Account” signal of FIG. 10r, the counter 75.1-75.p of block 6 of FIG. 7 goes into the state of the counting mode. Signal signals from output 18-20 of the monitored device are converted into normalized signals through single vibrators 45.1 and 45.2, element 2I 46.1 and 2-2I-OR-NOT 44.2 of block 1 of FIG. 2, which are fed to the clock input of counter 75 of block 6 of FIG. 7. When forming the transfer from the output of counter 75, IK-flip-flops 76.1 and 76.2 through element 2I 77.1 go into the activity state of the sign “Number found”, which is transmitted through the group of 24 outputs of block 6 to the first and second input of elements 46.2 and 46.3, to the first input element 2I 46.6 to the first inputs of elements 2 OR 48.1 and 49.4 block 1 of figure 2. As a result, at the second or third inputs of element 2-2I-OR-NOT 44.3 and 44.4, a permission signal is generated for passing information signals from the controlled device and permission to measure the value of time intervals at the input 34 of the first and second blocks - shapers 2.

 The recording mode in RAM 64 of block 4 of figure 5 is carried out in accordance with the time diagram of figure 11. Figa corresponds to the task of the functional mode of permission to play on the block (output 9, 10), and Fig.11b, c, d correspond to the signs of movement. TAX, block (outputs 20, 22, 18). On figl reflects the process of forming the sign "Number found" (output. IK-triggers 76.1 and 76.2 of block 6). On fig.11e shows the information output of the monitored device through two channels (output 21-23).

 Information signals through two independent channels in recording mode come from block 1 to the inverse and direct inputs of single-shots 50.1 and 50.2 of the first and second blocks 2. A shift of Fig. 11g is generated on the D-trigger to organize a normalized recording pulse through element 2I 56 and NOT 57, through the element 2I 65.11, 2 OR 66.1, NOT 67, 2 OR 65.2 in RAM 64 of the first and second block 4 of Fig.11z. From the output of the D-flip-flop 51 of the first and second blocks 3, a signal shifted by several clock cycles (clocking is from the synchronization block at the input 26 of the block) is sent to a single-shot 50.3 and then through a delay element 58 (standard RC chain) and through element 4I 55, 2I 53.2 to the clock input and, accordingly, the reset input of the K-trigger 52 in order to create a normalized load pulse of zero code combination by the clock pulse of the counter 60 of the first and second blocks 3 of Fig.11i. The value of the measured pulse through the bus driver 61, calculated clock pulses (outputs 29 and 28 of the synchronization unit 7) received at the clock input of the first and second blocks 3, respectively, are recorded sequentially at the address selected by the counter 63 of the first and second block 4. As a result, in RAM 64 creates an information array through two independent channels.

 The transition to the reading mode of the information array from RAM 64 is carried out in accordance with the interrogation of the microcomputer sign "Buffer full" according to output 17 of the device of FIG. 10c, t. The signal “Buffer full of I and II channels” is formed independently of each other by transfer activity from the outputs of the counter 63 of the first and second blocks 4 of FIG. 5. The transfer flag puts the RAM 64 into read mode through the IK-trigger 62, through the element 2 OR 66.2 blocks the IK-triggers 52 of the first and second block 2 and the one-shots 45.1 and 45.2 of block 1.

) и O(

) соответствующие первому и второму каналам. Далее программно решаются проблемы статистического анализа и оценки работоспособности устройства, в том числе выявление источника возмущения рассогласования сигналов по двум каналам, фиг.10ч и фрагмент распечатки фиг.12 с подсчетом M(x), D(х), моды, медианы и т.д. В программе предусмотрен повторный запуск относительно другого служебного сигнала и любого произвольного номера (переход 2 фиг.10ш). Если нет такой необходимости, то осуществляется переход на окончание процесса работы с микро-ЭВМ и контролируемым устройством фиг.10ш.The process of reading information from RAM is carried out in accordance with FIG. 10u-sh under the control of a microcomputer with its outputs 15-16. At the output 15, the microcomputer generates a clock signal that enters the counting input of the counter 63 through the elements 2 OR 66.1 and NOT 67. At the control input of the RAM element 64, the sign of reading from the output of the IK trigger is set, which is charged by overflowing the counter 62 in the information recording mode in RAM 64 of the first and second block 4. As a result, the corresponding address is set on the information output of the counter 63, which goes to the address input of the OP 64, which selects the information word, which in turn is transmitted in the form of the first and second formation group 39 to the information input of the multiplexers 68 of block 5. Reading the word bit by bit at the selected address is carried out under the control of micro-computers at the output 16 of Fig.10f. The clock pulse arrives at the counting input of the counter NOT 7 69, the information outputs of which, one of which is connected to the counting input NOT 5 70, and the outputs of the decoder 71 of block 5 control the multiplexer 68 during sequential bit reading of information on output 17 in the microcomputer. The information recorded in the array A of Fig. 10x micro-computer is divided by the programmer into arrays L (

) and O (

) corresponding to the first and second channels. Further, the software solves the problems of statistical analysis and evaluating the operability of the device, including identifying the source of the disturbance of the signal mismatch in two channels, Fig.10h and a fragment of the printout of Fig.12 with the calculation of M (x), D (x), mode, median, etc. d. The program provides for a restart against another service signal and any arbitrary number (transition 2 of Fig. 10sh). If there is no such need, then the transition to the end of the process of working with a microcomputer and a controlled device of Fig. 10sh is carried out.

 Technical appraisal and economic advantages of the claimed technical solution expanding the functionality of the proposed device (namely: improving the accuracy of control of the measured values, with their representation in digital form, signals arriving in the form of any code combination both continuously and discretely (block by block), increasing information content with subsequent statistical processing, in a microcomputer, by ensuring the registration of the values of the measured time intervals of the monitored signals on independent channels relative but the service signal with a specific number is determined by the combination of technical means used in the device and the new organization of communications.

Claims (1)

 DEVICE FOR DIAGNOSTIC CONTROL OF THE PLAYBACK CHANNEL OF THE DIGITAL MAGNETIC RECORDING INSTRUMENT a unit for measuring time intervals, a unit for generating a reset pulse, the output of which is connected to a reset input of a read unit, the first registration unit, characterized in that, in order to increase the accuracy and information content of the control via independent channels with respect to the service control signal, a second block of drivers, a second block for measuring time intervals, a second block of registration, a number selection block, a synchronization block and a system block are introduced into it of the control and processing unit, the reading unit is made two-channel, and the switch unit is made with the second and third inputs of the mode selection, the unit for generating the reset pulse with the reset input, the first block revolutionaries - with a mode selection input, which together with the first input of the mode selection block of the number selection block, a mode selection input of the second shaper block, connected to the mode selection input of the first shaper block, clock inputs of the registration blocks and a reading block, the first switch mode block selection mode input connected to the first input of the mode selection of the synchronization block are a group of control inputs of the device associated with the corresponding control outputs of the system control and processing unit, input p initialization confirmation of which is connected to the information output of the reading unit, the first, second and third control inputs, the first, second and third information inputs of the switch unit are, respectively, groups of service and information inputs of the device associated with a controlled playback channel of digital magnetic recording equipment, the switch unit is made with a group of inputs of a feature of a number connected to a group of inputs of a feature of a number of a unit for selecting a number whose reset input is connected to a reset input of a block reading, with the first reset input of the switch block, with the reset inputs of the first and second blocks of the drivers, the first and second blocks of registration, the first clock input - with the first output of the synchronization block and with the clock inputs of the first and second blocks of the drivers, the second mode selection input - with the second output of the switch unit and with the second input of the mode selection of the synchronization unit, the second and third outputs of which are connected to the clock inputs of the first and second time interval measurement units, and the fourth and fifth the th outputs are a group of control outputs of the device, the third output of the switch block is connected to the second clock input of the number selection block, the input of the reset flag of which is connected to the fourth output of the switch block, the fifth information output of which is connected to the information input of the second block of formers, and the sixth and seventh outputs service inputs of the first and second blocks of the shapers, respectively, the first outputs of which are connected to the inputs of the signs of loading, respectively, of the first and second measurement blocks time intervals, the groups of information outputs of which are connected to the groups of information inputs of the first and second recording units, the outputs of buffer filling signs of which are connected to the inputs of signs of the first and second blocks of the drivers, respectively, and the groups of inputs of the signs of buffer filling of the first and second channels of the reading unit, the output of signs the buffer filling of which is connected to the second reset input of the switch block, the first and second groups of information inputs of the read block The inputs are connected to the groups of information outputs of the respective recording units, the output of the recording characteristic of which is connected to the second outputs of the first and second blocks of the shapers, respectively, the inputs of the transfer signs of which are connected to the outputs of the first and second blocks of measuring time intervals, the control inputs of which are connected to the third outputs of the first and the second blocks of the shapers, while the synchronization block is made in the form of a counter, a clock generator, element 2 - 2I - OR - NOT, the AND element and the switch, the output of the clock generator is connected to the clock input of the counter, through the first group of the switch - with one input of the AND element, with the third input of the element 2 - 2I - OR - NOT and is the third output of the synchronization unit, the first output of the counter through the second group of the switch connected to another input of the element And is the first output of the synchronization unit, the fourth and fifth outputs of which are the third and fourth outputs of the counter, the output of the element And is connected to the second input of the element 2 - 2 AND - OR - NOT, the first the fourth inputs of which are the first and second inputs of the mode selection, respectively, and the output is the second output of the synchronization block, the number selection block contains two counters, two JK-triggers, two AND elements, AND element - NOT, NOT element, resistor block, indicator and switch through the corresponding contact groups of which the clock inputs of the first counter are connected to the zero potential bus, the groups of outputs of which are connected through the corresponding resistors of the resistor block with the corresponding indicators and connected to the input group in the data of the second counter, the input of the loading sign of which is connected to one input of the first AND element and to the output of the element NOT, the input of which is the first input of the mode selection of the number selection unit, the output of the transfer indicator of the second counter is connected to another input of the first AND element, the output of which is connected to the clock input of the second JK trigger, the clock input of the first JK trigger is connected to the output of the AND - NOT element, one input of which is connected to the direct output of the second JK trigger, and the other input is the first clock input of the select block RA, K-inputs and J-inputs of JK-triggers are connected to the buses of zero and unit potentials, respectively, the direct output of the first JK-trigger is connected to one input of the second element And, the other input of which is the second input of the mode selection of the number selection block, the inverse output of the second The JK trigger is connected to the subtracting clock input of the second counter, the summing clock input of which is the second clock input of the number selection block, the output of the reset flag of which is the reset input of the second JK trigger, the reset input is the inputs To reset the first counter, the reset inputs of which are connected to the zero potential bus, and the group of outputs of the number indicator contains the direct and inverse outputs of the second JK trigger and the output of the second AND element, the switch unit contains five elements NOT, four elements 2 - 2 AND - OR - NOT , two single vibrators, eight elements 2I, element 2I - NOT, three elements 2 OR - NOT, four elements 2 OR, input of the first element NOT and the first input of the third element 2I, input of the second element NOT and the third input of the first element 2 - 2И - OR - NOT, the input of the third element is NOT and the third input is second of the second element 2 - 2I - OR - are NOT respectively the first, second and third inputs of the mode selection of the switch unit, the input of the fourth element is NOT and the fourth input of the first element 2 - 2I - OR - NOT, the first input of the first element 2 - 2I - OR - NOT , the first input of the first element 2I are the first, second and third control inputs of the switch unit, the first input of the second element 2 OR is NOT, the second input of the first element 2I, the first input of the third element 2 OR is NOT the first, second and third information inputs respectively As the switch, the first input of the fourth element 2I is the first input of the reset of the switch unit, the inputs of the reset of the first and second single vibrators are the second input of the reset of the switch unit, the first input of the second element 2I and the second input of the third element 2I, the first input of the sixth element 2I, the first input of the first element 2 OR - NOT and the fourth element 2OR is a group of inputs of the sign of the number of the block of the switch, the output of the first element is NOT connected to the second input of the second element 2I, the sixth element 2I, to the first input of the fifth element 2I is the second output of the switch unit; the output of the second element is NOT connected to the second input of the first element 2 - 2I - OR - NOT, and the output of the third element is NOT connected to the first input of the second element 2 - 2I - OR - NOT, the outputs of which are connected to the first and the second inverse inputs of the first and second one-shots, the second inverse and first inputs of which are connected respectively to the bus of zero and unit potential and to the input of the fifth element NOT, the output of which is the third output of the switch unit, the output of the fourth element is NOT connected with the second and inputs of the elements 2 OR - NOT, 2 OR, the outputs of which are connected to the second inputs of the second and third elements 2 OR - NOT and the first inputs of the seventh and eighth elements 2I, and respectively with the second input of the fifth element And, the output of which is connected to the first input of the first OR element, the output of which is the sixth output of the switch unit, and the output of the fourth element 2 OR is the seventh output of the switch unit, the outputs of the first and second single vibrators are connected to the second input of the second element 2 - 2I - OR - NOT, and accordingly the first input of the 2I element is NOT, the second input of which is connected to the output of the second 2I element, and the output is connected to the second input of the fourth 2I element, the output of which is the fourth output of the switch unit, the output of the first 2I element is connected to the fourth input of the second element 2 - 2I - OR - NOT, to the second inputs of the seventh and eighth elements 2I and to the first input of the third element 2 - 2I - OR - NOT, the second input of which is connected to the output of the third element 2I, connected to the second input of the first element 2 OR and to the second input of the fourth element 2 - 2 AND - OR - NOT, the third input of the third element 2 - 2I - OR - NOT connected to the output of the sixth element 2I and the third input of the fourth element 2 - 2I - OR - NOT, the first and fourth inputs of which and the fourth input of the third element 2 2I - OR - NOT connected respectively with the outputs of the third and second elements 2OR, the first outputs of which are connected respectively to the outputs of the third and second elements 2OR - NOT, and the second inputs - respectively, the outputs of the eighth and seventh elements 2I, the outputs of the third and fourth elements 2 - 2I - OR - are NOT first and fifth By the output outputs of the switch unit, each driver unit contains three one-shots, a D-trigger, a JK-trigger, an OR element, three AND elements, an AND element NOT, an element NOT, a resistor and a capacitor, the first inverse and second inputs of the first and second one-shots are information the input of the driver unit, the reset input of the second one-shot is connected to the output of the first element And, the two inputs of which are the mode selection input and the reset input of the driver unit, the input is the first and second inverse inputs of the first and second one-shots with buses of unit and zero potentials, and the outputs are connected via an OR element to one input of the AND - NOT element and the data input of the D-trigger, the clock input of which is the clock input of the driver unit, the third data output of the D-trigger is connected to the first input of the third one-shot, the second inverse input of which is connected to the zero potential bus; the third inverse data output of the D-flip-flop is connected to the other input of the AND element - NOT, the output of which is connected to the input of the element NOT and is the third output of the shaper unit directly the output of the third one-shot is connected to the combined terminals of the resistor and capacitor and to the clock input of the JK trigger, the inverse output is to the first input of the third AND element, the output of which is connected through the second And element to the reset input of the JK trigger, the first and second information inputs of which and others the findings of the resistor and capacitor are connected respectively to the buses of unit and zero potentials, the output of the JK trigger is the first output of the driver unit, the output of the element is NOT the second output of the driver unit, input the transfer sign, the input of the sign and the service input of which is another input of the second element And and the second, third inputs of the third element And, respectively, the fourth input of which is connected to the reset input of the first one-shot, each unit for measuring time intervals is made in the form of a counter and bus driver, a group of inputs which is connected to the group of outputs of the counter, the group of data inputs of which is connected to the zero potential bus, the transfer outputs are the output of the transfer indicator shafts, the group of information outputs of which is the group of outputs of the bus driver, the control input is the input of the control indicator of the bus driver, the input of the download attribute is the write-read input of the counter, and the clock input is the clock input of the counter, each registration unit contains a JK trigger, counter, element random access memory, two AND elements, two OR elements, and the NOT element, the counter data inputs are connected to the zero potential bus, to which the J and K inputs of the JK trigger are connected, whose clock input is connected with the output of the counter transfer indicator and is connected to one input of the first AND element, the output of which is connected to the download input of the code combination data input of the counter, the group of outputs of which is connected to the group of address inputs of the random access memory element, the input of which is the reading record attribute is connected through the first OR element with a direct output of the JK trigger, and the group of outputs is the group of information inputs and outputs of the registration unit, the output of the buffer filling sign of which is the inverse output of JK- a trigger connected through the second AND element, the second OR element, the output of which is connected to another input of the first OR element, and the NOT element to the totalizing clock input of the counter, and the reset input of the JK trigger is connected to the other input of the first AND element and is the reset input of the registration unit , an input of the recording characteristic, the clock input and the output of the buffer filling characteristic of which are respectively another input of the second AND element, another input of the second OR element and the inverse output of the JK trigger, the reading unit contains a multiplex p, two counters, a decoder, an OR element - NOT and an element NOT, an output of an OR element - NOT connected to the first input of the multiplexer and is the output of the buffer fill indicator of the reading unit, the first and second groups of information inputs of which are the groups of corresponding information inputs of the multiplexer, the group of outputs which is the information output of the reading unit, the group of inputs of the sign of buffer filling of the first and second channels of which are the corresponding inputs of the element OR - NOT, the data inputs of the first of the counter are connected to the zero potential bus, the reset input is connected to the reset input of the second counter and the output of the element NOT, the input of which is the reset input of the reading unit, whose clock input is the summing clock input of the first counter, the outputs of which are connected to the multiplexer installation inputs, and the second output connected to the clock input of the second counter, the first and second outputs of which are connected to the first and second information inputs, respectively, of the decoder, the first inverse and second control inputs to they are connected to the third output of the second counter, and the second inverse and first inputs are connected to the zero potential bus, and the outputs are connected to the corresponding inputs of the multiplexer control attribute groups, the reset pulse generating unit is made in the form of an AND - NOT element, a resistor, and a capacitor connected in series between buses of unit and zero potentials, other interconnected terminals of the resistor and capacitor are connected to one terminal of the AND element - NOT, the other input and output of which are but the reset input and the output of the reset pulse forming.

Images