SU1624659A1 - Timed clock generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used to improve the accuracy of a synchronized clock generator. The purpose of the invention is achieved by introducing into the device a demultiplexer 2 and a normalization element 3. In addition, the device contains a quartz oscillator 1. When a synchronizing signal is applied, the quartz oscillator 1 is synchronized with output pulses of the normalization element 3, at a constant logical signal level at the input of the device at the output of the normalization element 3, a single signal is generated. to free generation mode without changing the duration of the device output pulses beyond the specified limits. 1 silt

Description

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The invention relates to a pulse technique and can be used to synchronize automation devices and computing devices.

The aim of the invention is to improve the accuracy of the synchronized clock generator.

The drawing shows a functional diagram of a synchronized clock generator.

The device contains a crystal oscillator 1, a demultiplexer 2, a normalization element 3, an output value 4, a clock signal and control bus 5. Quartz oscillator 1 contains the first 7 and second 8 elements AND –NE, the inverter 9, the first JO and the second 11 clock inputs, the first 12 and second 13 resistors, the crystal resonator 14. The normalization element 3 contains the delay element 15, the third 16, the fourth 17 and fifth. 18 elements AND NOT.

Bus 5 of the clock signal is connected to the input of the normalization element 3, the output of which is connected to the information input of the demultiplexer 2, whose address input is the control bus 6, and the first and second outputs are connected to the first 10 and second 11 clock inputs of the crystal oscillator 1, respectively the output of which is the output bus 4 of the device.

The first 12 and second 13 resistors are connected between the first inputs and outputs, respectively, of the first 7 and second 8 NAND elements, the second inputs of which are respectively the first 10 and second AND synchronization inputs of the quartz oscillator 1, the quartz resonator 14 of which is connected between the first input of the first element NAND 7 and the output of the second element NAND 8 connected to the input of the inverter 9, the output of which is the output of the quartz oscillator 1. The output of the first element NAND 7 is connected to the first input of the second element NAND 8,

The inputs of the normalization element 3 are the first inputs of the third 16 and fifth 18 NAND elements, the second inputs of which are connected respectively to the outputs of the delay element 15 and the fourth AND NAND 17 element, the first input of which is connected to the output of the third AND 16 NOT element to the exit

0

five

normalization element 3, the second input of the fourth element AND-NOT 17 is connected to the input of the delay element 15 and to the output of the fifth element AND-NOT 18.

The device works as follows.

When the supply voltage and the corresponding signal are applied to the bus 6, the crystal oscillator 1 is energized and a sequence of frequency pulses fc is formed on the output bus 4. The synchronizing signals of the frequency f are generated. with a pulse duration t, is fed to the input of the element 3 valuation. When a clock pause (O) arrives, the AND-NE elements 16, 18 are switched to one state, and the AND-HE element 17 is set to zero. With the arrival of the positive half-wave, the element AND-16 is transferred to the zero state. The time of the element AND-EO 16 in the zero state is defined as

4 + t, l (18) + t. (15) +

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(17)

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+ t

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(16) Ј l / 2f0- / 4fo,

where t

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04

-time of transition from state 1 to O (inclusion);

- transition time from O to 1 (off);

five

0

five

t, the time due to the delay element 15.

Under actual conditions, when organizing external synchronization, it is necessary to realize certain phase relations between the synchronization signal f- and the output signals. This is achieved by connecting the normalization element 3 with the help of the demultiplexer 2 either to the first 10 or to the second 11 clock inputs of the crystal oscillator 1. This takes into account that the normalizing signal is generated on the front of the signals f. If a source of a sync signal of type O or 1 fails, the output of the normalization element 3 is set to I and the master oscillator is operating at its own frequency f0.

When applying to the diagnostic input (the resolution input of demultiplexer 2 is not shown) of a signal that converts the demultiplexer 2 to the third state, the crystal oscillator 1 switches to its own frequency fQ, which allows, without disconnecting the source of the synchronizing signal, to produce

check the natural frequency fe of the crystal oscillator 1 and, if necessary, carry out its adjustment.

Thus, the accuracy of the device is improved by keeping the device’s output pulses within a predetermined range and the synchronizing signal disappearing.

Claims (2)

1. A synchronized clock oscillator containing a crystal oscillator whose output is an output bus of a device, characterized in that, in order to increase the accuracy of operation, a demultiplexer and a normalization element are inputted into it, and the output is connected to the information input of a demultiplexer, whose address input is 0 control device t and the first and second outputs are connected respectively to the first and second clock inputs of the crystal oscillator. 2. Generator pop. 1, which differs from the fact that the normalization element contains a delay element, the first, second and third elements of NAND, the input of the normalization device is connected to the first inputs of the first and third elements of NAND, the second inputs of which connected respectively to the outputs of the delay element and the second element H-NOT, the first input of which is connected to the output of the first AND element and the output of the normalization element, the second input of the second AND-element is connected to the output of the third AND element and to the input of the delay element.