SU819967A1 - Controllable repetition rate skaler - Google Patents

Description

one

The invention relates to a pulse technique and can be used in measurement technology and automation.

A pulse frequency divider is known, containing a counter, two elements of coincidence, an OR element, and an additional frequency generator, the change in the division factor of which is based on eliminating input pulses and adding additional frequency signals that are offset from the input pulses I between the input pulses.

However, the need to introduce additional frequency leads to low speed.

The closest to the technical essence of the invention is a pulse frequency divider with a variable division factor, comprising a frequency divider, a reference oscillator, a control unit containing a calibrator, an OR element, a coincidence element, the first inputs of which are connected to the output of the reference oscillator, the second inputs of the first and the second element of the match with the output of the calibrator, the second input of the third element of the match with the output of the second element of the match, and the output of the third element of the match is connected to the first in element OR, the second input of which is connected to the output of the first bit of the frequency divider, and the output to the second bit input of the frequency divider, while the second input of the second coincidence element is connected to the correction sign spine, the calibrator input to the correction resolution bus, and the output of the first element And is connected to the inputs of the first bit of the frequency divider 2.

The aim of the invention is to increase speed.

Claims (2)

This is achieved in that a controlled pulse frequency divider containing a frequency divider consisting of a T-flip-flop and a pulse counter, and a control unit, the first, second and third inputs of which are connected to the input panel, the correction resolution and the sign of the correction, respectively. , and the first and second outputs respectively to the counting inputs of the T-flip-flop and the pulse counter of the frequency divider, the fourth input-control unit is connected to the output of the T-flip-flop and the additional counting input of the pulse counter of the frequency divider, i The synchronization codes of which are connected to the input bus, while the control unit contains DV trigger, 8O-mp / igger and O-trigger, the synchronization inputs of which are connected to the input bus and are the first input of the rectifier unit, the controlled input of the DV trigger, The fourth input of the control unit is connected to the output of the T-trigger of the frequency divider, the information input, which is the second input of the control unit, to the correction resolution bus. and the output with the information input Dtrigger and the first information inputs of the first and second 8O-flip-flops, the second information inputs of which are connected to the inverse output of the D-flip-flop, and the inverse outputs of the first and second 8U-triggers, which are the first and second outputs of the control unit are connected to the counting one the input of the T-flip-flop and an additional counting input of the pulse counter of the frequency divider, while the third information input of the second 8D trigger is the third input of the control unit. The figure shows a jet An electrical circuit device. It contains frequency divider 1, control unit 2, pulse counter 3, T-flip-flop 4, 8O-flip-flops 5, 6, DV-flip-flop 7; D trigger 8, bus 9 input, bus 10 resolution correction, tire 11 of the sign of the correction. In the absence of a signal on the bus 10, the device performs the functions of a frequency divider with a division factor Ka. With the appearance of the signal on bus 10, the DV flip-flop 7 applies it to the input frequency f |. at times when the T-flip-flop 4 is in a single state. This imposes a limitation on the signal “correction resolution, the duration of which must be at least 2.5g- (with a duty cycle of the input frequency equal to two). The received signal is delayed by one period of the input frequency to further isolate the leading edge from it, which is fixed in SD-TpHrrepe 5 and, if there is a signal on bus 11, in 8D-TpHrrepe 6. The inverse signal from the output 8D-TpHrrepa 5 stops T -trigger 4. If the signal on the bus 11 is absent. then, at the output of the 8D-TpHrrepa 6, there is a "unit" and a change in the so-called counter 3 is made, which is equivalent to a reduction in the division factor by "unit (addition). The presence of a signal on the bus 11 causes the counter 3 to stop for one period of the input frequency. This is equivalent to increasing the division factor by "one" (exception). The introduction of new elements and the connections between them allows to increase the speed of the device. Claims. A controlled pulse frequency divider, containing a frequency divider consisting of a T-flip-flop and a pulse counter, and a control unit, the first one. The second and third inputs of which are connected respectively to the input bus, correction resolution gaps and correction marks, and the first and second outputs respectively to the counting inputs of the T-flip-flop and pulse counter, a frequency divider, characterized in that, in order to improve speed, the fourth input The control unit is connected to the output of the T-flip-flop and an additional counting input of the pulse counter of the frequency divider, the synchronization inputs of which are connected to the input bus. 2. The divider according to claim 1, wherein the control unit comprises a DV trigger, 8O trigger and a D trigger, whose synchronization inputs are connected to the input bus and are the first input of the control unit, the control input of the DV trigger, The fourth input of the control unit is connected to the output of the T-flip-flop of the frequency divider, the information input, which is the second input of the control unit, with the resolution of the corrector. response, and the output - with the information input of the D-trigger and the first information inputs of the first and second 8D-triggers, the second information inputs of which are connected to the inverse output of the Trigger, and the inverse outputs of the first and second 8D-TpHrrepOB, which are the first and second outputs of the control unit , are connected respectively to the T-flip-flop input and an additional counting input of the pulse counter of the frequency divider, while the third information input of the second 8D trigger is the third input of the control unit, Information sources, N same as defined in the examination note 1. Martynov EM synchronization in digital communications transmission systems, M., bond, 1972, p. 15-18. 2. USSR author's certificate No. 455497, cl. H 03 K 25/04, 02/23/73.