SU1617645A1 - Multichannel data transceiving system - Google Patents

Abstract

The invention relates to radio engineering and communication technology, in particular to multichannel telemetry systems. The aim of the invention is to improve noise immunity. The multichannel system contains on the transmitting side: N information sources, N matching blocks, N switches, N totalizers, seal block, distributor, counting trigger, clock generator, reference voltage source, voltage divider, two calibration voltage blocks, N elements delays, N inverters, and on the receiving side: three amplitude detectors, N + 4 adders, dividing unit, voltage divider, N + 1 comparators, decoder, equivalence element, dividing unit, N receive channels, each of which includes flushes a receiver, the two flip-flop, two memory element, two adders, a switch, four monostable, demodulator. The goal is achieved by the fact that each sample of channel signals is transmitted by a pair of samples of equal size and opposite in sign, i.e. the modulation index of the PAM signals in this system is two times higher than in the known system. 3 il.

Description

The invention relates to radio engineering and communication technology, in particular to multichannel telemetry systems.

The aim of the invention is to improve the noise immunity.

FIG. 1 shows a block diagram of the device on the transmission, to her side; in fig. 2 - the same on the receiving side; in fig. 3 - voltage plots showing the operation of the device.

The multichannel system for transmitting and receiving information contains on the transmitting side (Fig. 1) N information sources 1, N matching units 2, N first switches 3, N adders 4, compacting unit 5, distributor 6, counting trigger 7, clock generator 8, source 9 of the reference voltage, the first voltage divider 0, the first 1 and second 12 blocks of the calibration voltage, N delay elements 13, N inverters 14, and the first 15, second and 16 17 amplitude detectors, first 18, second 19 and third 20 additional adders, dividing unit 21, fourth additional adder 22, the second divides & n 23, N comparators 24, additional comparator 25, decoder 26, equivalence element 27, N adders 28, separation unit 29, N reception channels 30, each of which includes receiver 31, the first trigger 32, the second trigger 33, the first 34 and the second 35 elements of the network, the fifth 36 and the sixth 37 add additional adders, the second switch 38, the first 39, the second 40, the third 4 -1 and fourth 42 one-shot and demodulator 43.

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Multichannel system of transmission and reception of information 1.i works as follows.

Information signals from the sources of pestun ya ma 2 blocks of matching, where the equalization of the amplitudes of the signals of different channels and the compression of the dynamic range of the signal occurs. Thus, at the outputs of the matching unit 2, signals are obtained, the maximum sweeps of which are equal to each other. Then these signals arrive at the first inputs of the first switches 3, the second inputs of which are received the same, but delayed by 1h and inverted signals. As a result, at the outputs of the first switches 3, a sequence of bnpols of p1 of amilite-modulated pulses is obtained, the bunches of positive and negative pulses have equal amplitudes and the first of the pulses in the pair corresponds to the direct signal from the output of block 2, and the second to the delayed inverse. Next, the received signals are summed in adders 4 with constant voltages differing in magnitude and (or) in sign, which are fed to the second inputs of adders 4 from the first divides 10 voltages. The magnitudes of the voltage of the reference source 9 and the resistance of the first decoupler 10 are chosen such that the outputs of the sum of the sensors 4 produce voltages in the ranges that do not overlap with each other at Eipo-arbitrary signals at the outputs of the matching unit 2. Next, the voltages from the outputs of the adders 4 and the first 1 and second 12 blocks of the calibration voltage are sent to the information1 :: ioh inputs of the block 5.} is dense, cohort under the action of control signals produced by the frg-limiter 6 of the signals with frequency t / 2 ( resulting at the output of the counting trigger 7), produces the group signal. As a result, at the input of Alok 5, a bipolar group signal Urn is obtained in the form of a figure of a figure, and the amplitudes W (body and otchtitelnyh directions; group C1 will turn out to be equal; om and A and constant in BpeNieH i, and e-; voltage gates corresponding to different channels, group strings: it turns out to be symmetrical about the corresponding reference stress and its span is equal to twice the value of the corresponding reference.

Formation of a group signal by the example of a three-site system is shown in FIG. 3. In Kachech: your informational signals are used in the first channel of a sinusoid (Fig. 3, a), in the second - the cosine curve (Fig. 3, b), in the third - the exponent (rt games 3, c). Swings of all signals do not exceed and. Further, the discrete values of the forward and delayed 1П1verse C5; n; 1

five

five

from the outputs of the first switches 3 are summed by adders 4 with constant voltages taken from the first divider 10: the signals of the first channel are with voltage and + Li, the signals of the second channel are with zero voltage, the signals of the third channel are with voltage - (Uj-AU), where AU is the voltage spacing, and is fed to the second, third, and fourth inputs of the compacting unit 5. Constant voltages 3/2 (U + AU) + AU / 2 are fed to the first and fifth inputs of block 5 through the first II and second 12 blocks of the calibration voltage.

(and + di) + di / 2. As a result, the output of block 5 forms the group signal shown in FIG. , 3,

Further, the Urp group signal passes through the communication line, where additive Ua and multiplicative Ua interferences are added to it, forming the distorted signal Un Urp (l-f - | --U) + Ua. The envelopes of the positive and negative amplitudes of the distorted group signal are extracted by the first 16 and second 17 amplitude detectors, the outputs of which are (l-tLU) + U. and (l + 0) voltages and where - voltages of multiplicative and additive interferences, respectively, that are fitted over samples with a sampling interval of 2 (N + 2) / fT. At the output of the third additional (subtractive) adder 20, an LJ2o additive interference signal () is generated, and at the output of the second additional adder 19, the multiplier interference signal Uig ((- | -Um) As a result, the output of the first additional adder 18 is received

and., 8 1. Un-f 0, (1 -f Urn) + Ua --- U.

-Urp (lf Um) + uUo, and at the output of cellen block 21 - si t; al U2i Ui8 / KUi9 Urp (+ -f and „,) / К2А (1 -Ь U; n) + Lie„ / К2А () where} (-, og gunn a block of 21 cases.

For interference with the correlation interval (N + 2) / fT, the voltage J, and From, recovered from the samples, coincide with Uc and Urn, and the voltage U2i takes the form U2i Urp / K2A, i.e. with accuracy to a constant multiplier} the n-el coincides with the original group signal at the output of block 5.

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In the presence of add-on interference, the corre. which (N-j-2) / Fr, the signal at the output of dividing unit 21 contains an additive noise, which reduces the noise immunity of the system and violates its

work FIG. 3 shows an example of such an interference; FIG. 3, e is the change of the group signal under the action of interference, and by f. G. 3, g is the signal at the output of the dividing unit 21. From FIG. 3, it is seen that, under the influence of a weakly correlated interference, the symmetry of the group signal with respect to the reference voltages is violated, and transitions to the voltage intervals belonging to adjacent channels are observed.

Further, the partially (or completely) cleaned group signal through the (N- | -l) -Bxo- additional fourth additional adder 22, in which additive interference with correlation interval is compensated, is fed to the first amplitude detector 15. From its output voltage equal to the span of the group signal, with the help of the second voltage divider 23, N reference voltages are formed, with respect to which the information signals are shifted, and N-fl voltages of the boundaries between the intervals of the corresponding channel voltages. The resulting reference voltages are summed with the group signal by the adders 28, at the outputs of which the group signal is shifted (by the amount of the reference voltage) so that the voltage interval belonging to this channel is symmetrical with respect to the zero voltage. The comparator 24 and the additional comparator 25 compare the group signal with N + 1 interval boundary voltages and, through the de- finer 26, turn on the corresponding bit of the separation unit 29 for the time during which the voltage of the group signal at the output of the corresponding adder 28 is in the range of voltage of this channel. Thus, at the outputs of separation unit 29, pairs of bipolar pulses of equal (in the absence of additive interference) amplitudes are obtained, whose span is equal to twice the value of the corresponding channel count. In the presence of interference (as follows from Fig. 3), the pulses of positive and negative polarity have different amplitudes, with the difference of the amplitudes equal to twice the value of the interference at the time of reference. The positive edge of the control pulse of the block 29 of the corresponding reception channel 30 triggers the first single-oscillator 39, the output pulse of which with the duration ti clears (deletes) the contents of the first 34 and second 35 memory elements and resets the information from the second trigger 33 the first 34 and second 35 memory elements. The negative pulse front from the output of the first one-shot 39 initiates the second one-shot 40, the output

a pulse whose duration is t2 l / 2fr

Allows the entry in the first memory element 34 of the amplitude value of the first in a pair of (direct) counting pulses (recording is maintained for half the counting pulse length). The negative edge of the pulse from the output of the second one-vibrator 40 prohibits the recording of information in the first memory element 34 and after a time of 1 / 2Gt a single-signal 41 starts, whose output pulse with a duration of t3 1 / 2Gt allows the second amplitude value 35 in the memory element 35 to start up.

a pair of counting pulses that are associated with the delayed inverse signal (recording is maintained for half the counting pulse duration). A negative pulse front from the output of the third mono-vibrator 41 triggers the fourth one-shot 42 and prohibits the recording of information in the second memory element 35. By the positive front of the output pulse of the fourth one-shot 42, the second trigger 33 is transferred to the state “1”, which allows reading information from the first 34 and second 35 memory elements, and writing “1 to the first trigger 32, which allows the signal to pass through the second

switch 38. Thus, after starting the fourth one-shot 42 at the output of the fifth additional adder 36, there is a signal corresponding to twice the counted value of the information signal, which through the demodulator 43 sends to the receiver 31, and at the output of the inverting sixth additional adder 37 - the signal corresponding to the counting of the inverted additive field AND, which through the second switch 38 goes to one of the inputs of the fourth additional adder 22, performed the correction of the group with I drove on the next cycle. The sum correction signal is shown in FIG. 3, h. The interruption of the supply of correction signals at time intervals corresponding to the transmission of calibration signals (which are used to correct the baseband signal) is carried out by the second switches 38 under the influence of the signals "O at the outputs of the first triggers 32.

The first flip-flops 32 are transferred to the state "O" by the signal "i" from the output of the equivalence element 27, which occurs when calibrating voltages are received (all comparators are in "1 or" O). The signal plots at the outputs of the fifth additional adders 36 are shown in FIG. 3, ", to, l. Thus, after demodulation, undistorted information signals are obtained at the inputs of the receivers.

The noise immunity of the proposed system in the case of highly correlated interference ((N + 2) / fT is twice as high as in the prototype system, since the modulation index of the AIM signals (with the number of channels) in the proposed system is twice as high, than in the prototype system. In addition, the immunity of the prototype system decreases dramatically when exposed to interference with the correlation interval (N + 2) / fT,

 in the proposed system, the noise immunity remains unchanged for interference whose correlation interval (since the interference is restored at each cycle).

Claims (1)

Invention Formula A multichannel system for transmitting and receiving information, containing on the transmitting side N information sources, the outputs of which are connected to the inputs of the corresponding N matching blocks, 1V adders, the first inputs of which are connected to the corresponding outputs of a voltage divider, the inputs of which are connected to the outputs of the voltage source, and through the first and second blocks of the calibration voltage to the first and second extra inputs of the sealing block, the inputs of which are connected to the corresponding outputs of the adders, clock pulse and pulse distributor, the outputs of which are connected to the control inputs of the compacting unit, and on the receiving side - the first, second and third amplitude detectors, the first, second and third additional adders, dividing unit, N adders, whose outputs are connected to the corresponding inputs of the channel separation unit, N demodulators, the outputs of which are connected to the corresponding inputs of N receivers, N comparators, the first inputs of which are combined with the first inputs of the N adders and the input of the first amplitude detail the first and second outputs of which are connected to the corresponding inputs of the second voltage divider, whose N outputs are connected to the corresponding second inputs of N adders, the decoder whose outputs are connected to the corresponding control inputs of the channel separation unit, and the decoder inputs are connected to the outputs of the N comparators, the combined inputs of the second and third amplitude detectors are connected to the first input of the first additional adder, the output of which is connected to the first input of the division unit, second Its input is connected to the output of the second additional adder, the first and second inputs of which are combined with the corresponding inputs of the third additional adder are connected respectively to the outputs of the second and third amplitude detectors, and the output of the third additional adder is connected to the second input of the first additional adder, different the fact that, in order to increase noise immunity, on the transmitting side, the outputs of the matching blocks are connected to the second inputs of the corresponding N adders via entered in series connected delay elements, an inverter and the first switch, and the output of the clock pulse generator is connected to the input of the pulse distributor via an input counting trigger, whose input is combined with the control inputs of the N first switches, the second inputs of which are connected to the inputs of the corresponding delay elements, and at the receiving On the side, the output of the dividing unit is connected to the input of the first amplitude detector via the fourth input. an additional adder, the inputs of which are connected to the outputs of the entered N second switches, and the outputs of the channel separation unit are connected to the corresponding demodulators in each reception channel through serially connected first memory elements and fifth additional corers, and to the outputs of the decoder in each reception channel connected in series first, second, third and fourth one-shot, as well as the first trigger, the output of which is connected to the control input of the second switch, and the second trigger connected in series, the second memory element and the sixth additional adder are connected to each receive channel to the input of the second Switch, and the second voltage divider is equipped with N-f-l additional outputs connected respectively to the second inputs of the N comparators and the first input of the introduced additional comparator, the output of which, as well as the outputs of the N Comparators, is connected to the inputs of the equivalence element, the output of which is connected to the reset inputs of the first triggers, the installation inputs of which in each reception channel are combined with the installation input of the second trigger whose output is connected. . to the first control input of the first memory element, the second control input of which is combined with the second control input of the second memory element, the reset input of the second trigger and the input of the second one-oscillator, the output of which is connected to the third control input of the first memory element whose output connected to the second input of the sixth additional adder, and the outputs of the block channel separation is connected to the corresponding information inputs of the second memory element, the third control inputs and outputs of which in each reception channel are connected respectively to the output of the third one-shot and inverse the input of the fifth additional adder, and the second input of the additional comparator is combined with the first inputs of the comparators. Jr sh L 13 J ten g ii HP 1 0.5U 0}