SU1591026A1

SU1591026A1 - Device for interfacing computer with general-use channel

Info

Publication number: SU1591026A1
Application number: SU874305872A
Authority: SU
Inventors: Yurij G Ovechkin
Original assignee: Yurij G Ovechkin
Priority date: 1987-09-11
Filing date: 1987-09-11
Publication date: 1990-09-07

Description

The invention relates to computing and can be used in measuring systems having a common channel. The aim of the invention is to reduce the cost of computer time.

when implementing the polling function. The device contains a control unit 1, a counter 2, an operational storage unit 4, an address register 5, a transceiver 6, a control word register 7, a receiver synchronization unit 8, a transmitter synchronization unit 9, a synchronization unit 10, a receiver 11, a multiplexer 12 local messages, a decoder 13 , block 14 of the formation of a service request, the transmitter 15, the first register I / o 16, the register 17 of the status word, the second register 18 I / o. The device provides a sequential polling of the states of devices connected with it through the public channel and the transfer of information to the computer. / 2 Il. s

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The invention relates to computing and. Can be used in measurement and control systems that have a common channel.

The aim of the invention is to reduce the cost of computer time when implementing the function of sequential polling.

FIG. 1 is a block diagram of the device; in fig. 2 - control unit diagram.

The device (Fig. 1) contains a control unit 1, a counter 2, a computer 3, an operational storage unit 4, an address register 5, a transceiver 6, a control word register 7, a receiver synchronization unit 8, a transmitter synchronization unit 9, a synchronization unit 10, a receiver 11 , a multiplexer 12 local messages, a decoder 13, a service request generation unit 14, a transmitter 15, a first input / output register 16, a status word register 17 and a second input / output register 18.

The control unit 1 (Fig. 2) contains the first element NOT 19, the first element AND-NOT 20, the first 21 and the second 22 pulse shapers, the first trigger 23, the first element AND 24, the second element AND-NOT 25, the second element And 26, the third 27 and fourth 28 elements are NOT-NE, the third driver 29 pulses, the third element AND 30, the fourth driver 31 pulses, the second trigger 32, the fifth element AND-HE 33, the second element NOT 34, the first 35 and the second 36 elements OR, the fifth shaper 37 pulses, third trigger 38, sixth 39 - ninth 42 NAND elements, sixth shaper 43 pulses, third ele ment OR 44, fourth trigger 45, tenth element AND-NOT 46, fourth element AND 47, fourth element OR 48, decoder 49, fifth element OR 50, information output 51 of block, fifth 52 and dough 53 elements And, third 54 and fourth 55 elements NOT, the seventh element And 56, the seventh shaper 57 pulses, the eleventh element AND-NOT 58, the eighth element And 59, the output 60 block recording, the sixth element OR 61 / the ninth element And 62, the output 63 specifies the direction of transmission of the block, the twelfth element AND-NOT 64,

the fifth trigger is 65, the ninth element is And 66, and the sixth trigger is 67.

The device works as follows.

Preliminary, block 4 of the device’s memory is recorded in a sequential polling program. For this purpose, a zero level signal is applied to the "Record" input of the control unit 1. The signal "Record" level prohibits the formation at the output of the shaper 22 of the load signal on the input signal 30. At the same time, the signal "Record" is fed to the input element And 24, while at its output a signal ZP is generated. The signal of the RFP prohibits the device from forming local messages. At the same time, the "Record" signal sets the trigger 45 to the zero state. At the same time, the "Transmission direction T" signal is generated at the single output of the trigger 45, which is fed to the input of the transceiver 6 of the same name. The latter is transferred to the information input mode from the internal channel data channel to the device . The output "Output allowed" (OE) of the control unit through the element 47 is fed to the same input of the transceiver 6 signal of zero level. The data bus of the memory block 4 is connected to the internal data bus of the channel. Rear 'signal edge "Record" via AND-NO element 25 is supplied to the direct input of the ^29: to direct the output of which generates a signal "Reset", which is supplied to the counter input of the same name. The computer, using the output command, sets the code of the interface command "Inhibit sequential polling" (ZPO) at the output of the transceiver 6 and generates a negative impulse that arrives at the input of the OR 44 element, or the output of which generates the "Write resolution" signal (IE) the same input of block 4. This produces a signal · "Writing the interface command" of the ZPO to the zero memory cell. At the same time, this signal through the element OR 44 is fed to the input of the element AND-NO 46, at the output of which the signal "Tact" is formed, which is fed to the input of the same name of counter 2 and on the leading edge of the signal "Tact" increases its content by one, while the counter indicates the address of the first

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memory cells. Similarly, write to the first memory cell of the interface NAP command. The hexadecimal FGN code is written to the second memory cell, the code of the NPM interface command is written to the third memory cell, and the fourth is the code of the 0П0 interface command. In subsequent memory cells, the processor records the interface commands for the addresses of the system's sources to be polled. The maximum number of instrument controllers polled is 14. This completes the recording in the device’s memory. The processor, using the output command, removes the "Log.O" level from the "Record" input of the device. If the interface signal 30 is passive, i.e. At the input of the driver 57, there is a level "Log.1", then a negative pulse is formed on the rising edge of the signal "Record" at the inverse output of the driver 57, which through the element 59 goes to the information input of the counter 2. At the same time, a positive pulse from the direct output of the driver 57 through the element OR 48 is fed to the P input of the shaper 22. At the same time, at its inverse output a “Load” signal is generated, which is fed to the same input of counter 2, the second hexadecimal inputs are written to the counter 2 code 0211. The hexadecimal code 2H from the second memory cell enters the AO-Ab inputs of the decoder 49. At the same time, the following signals appear on the outputs of the last: on the first, second and fifth outputs the level "Log.1", on the third, fourth outputs - level "Log.O". The trigger 67 is set to zero. The level "Log.O" from the single output of the trigger 67 is fed to the input of the element AND 24. From the output of the element 24, the signal of the RFP is formed. This signal prevents the device from forming local messages. Control unit 1 comes to its original state. The block is reset to its initial state also by the interface signal OI. The signal OI level "Log.O" is fed to the information вход-input of the counter 2. A positive differential arrives at the direct input of the shaper 22, while the ZAGR signal is generated at the inverse output of the shaper 22, which, acting on the like-name.

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the second input of counter 2, writes to the hexadecimal counter

F2H values. In the control unit 1

CP signal is generated, which ^appa} rature control unit is reset. With the arrival of the signal 30 (or if, at the moment of transition of the signal "Record" from the level

hell "Log.O" in "Log.1" signal 30 is in the active state); the second input of the shaper 57 is supplied with the level "Log.0", prohibiting the formation of the signal ZAGR from the positive

15 differential signal "Record". At the same time, a positive differential arrives at the ϋ-input of the driver 22, while the signal ZAGR is generated at the output of the control unit 1. Going on

20 entry in the counter 2 hexadecimal values FZN. The code of the NPM interface command from the third memory cell is fed to the address inputs Λ0-Α6 of the decoder 49. At the same time, the first voltage levels are set to the first 25 second outputs, the third and fifth levels are set to "Log.O", and the first, second and fourth levels are set to .one". The signal level "Log.O" from the fifth output of the decoder 49 is fed to the input element And 53. At its output, a signal is generated local message. The trigger 67 is set to one. With the single input of the trigger 38 is removed the level of "Log.O". With the release of the element 24 is removed, the signal ZP. The level of "Log.O" from the zero output of the trigger 67 is fed to the ϋ-input of the driver 31. If

dd controller function K is in the η state of the SSC, the synchronization function of the source of the SI is in the CIGR state, and the trigger 23 is in the zero state, then the output element

45 and 26 a positive differential is formed, which is fed to the clock C-input of the trigger 32.

A positive difference at the C input of the trigger 32 at the beginning of each cycle of issuing the interface command code from memory verifies the presence of the interface signal 30. Moreover, if the signal 30 is removed before issuing the first interface command of the sequential polling contained in the third memory cell, the trigger 32 remains in a single state. The trigger 38 also remains in a single state. Positive differential with delay7 1591026

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Coy on the element 30 and enters the ϋ-input of 31. Thus on pryamom'vyhode shaper 31 is formed by a positive pulse, which via $ NOT elements 54 and ₅₅ is fed to AND-NO element 40, whose positive output of differential circuit element And 52, the element AND 64, the element OR 48 is fed to the ϋ-input of formation 22. A ZAGR pulse is formed, the hexadecimal code F2H is written to counter 2. The scheme of the control unit 1 is reset. Elemen, 5 'you And 30,54 and 55 are necessary to eliminate the logical states of the signals at the outputs of the elements AND-NOT 40 and 41.

If the signal 30 is removed in the issuance cycles of the interface commands, the trigger 20 32 is set to one state according to the signal at the clock input. A positive differential from a single output of the trigger 32 comes through the element OR 61 to the direct input of the shaper 21, from the inverse output of which a negative impulse goes to the element AND-NOT 25, the positive differential from the output of which is fed to the ϋ-input of the shaper 29, At the output - 30 de block 1 of the control signal is formed "Reset", which, acting on the same input of counter 2, sets the counter to zero position.

The contents of the zero memory cell are output from memory - the code of the ZPO interface command. At the output of the shaper 31, a leading pulse is generated from the output of the AND 26 element, and a positive pulse is applied to the 40 input of the AND-NOT element 39 and HE 54. and 55 to the input element AND-NOT 41. From the output of the element AND-NOT 39 a negative pulse arrives at the zero input of the trigger 38, confirming 45 its zero state. At the output of the element AND-NOT 41, a local INB message is generated. By a local INB message to the interfaces, the SI function is transferred from the CIGR state to the SIAD 50 state. At the same time, the INB signal sets the trigger 45 to the single state, while from the "Direction of forwarding, giving" (T) "Output allowed" (OE) of the control unit 1 the inputs 35 of the transceiver 6 of the same name are supplied with logical voltage levels "1" and "0", respectively. The transceiver 6 switches to the information output mode from

memory on the internal data bus Kong roller and then on the data bus LD0-LD7 KOP. The ZPO interface command enters the CPC data bus. At the same time, the local message signal of the INB records in the register 5 the addresses of the code of the ZPO interface command. On the leading edge of the LED signal, the trigger 45 is set to the zero state. In this case, the transceiver 6 disables the memory data bus from the internal data bus of the controller. At the same time, the leading edge of the SD signal at the output of the former 43 generates a negative impulse, which is outputted through the I-NE 46 element to the output "Tact" of the control unit 1. The rising edge of the “Tact” signal of counter 2 is incremented by one, indicating the address of the first memory cell containing the NAP interface command code. A NAP interface command is issued on the LDC-LD7 KOP data bus, at the end of the NAP command cycle, the contents of counter 2 is increased by one unit, i.e. becomes equal to 2. The circuit of the control unit 1 is reset.

If the signal 30 is not removed during the input of the NPM interface commands, 0П0, MAI, then the device operates as follows.

With the arrival of signal 30, the signal ZAGR is formed at the output of the control unit 1, the “Log.1” level is generated at the ϋ1-input, the hexadecimal code of the FZN is written into the counter 2. The code of the NPM interface command is selected from the memory of the control unit. At the outputs of the decoder 49, the following voltage levels are formed on the third and fifth - "0", on the remaining "1", the trigger 67 is transferred to the one state, the signal of the RFP is removed, the level Log.0 is removed from the single input of the trigger 32 ". A positive differential from the output element And 26 • trigger 32 is transferred to the zero state. At the output of the imaging unit 31, a positive pulse is generated, which, through the IS-NOT 39 element, is transmitted by the logic zero level to the zero input of the trigger 38, which is transferred to the zero state. Level "Log.1" from the zero output of the trigger 38 is fed to the element AND-NOT 41. With the arrival of a positive impulse

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from the direct output of the driver 31, at the output of the NAND 41 element, a signal of the local message INB is generated. The LDC-LD command code is issued to the LDC-LD7 data bus of the CPC.

◆ Positive * with the front of the SD signal, the signal “Tact” is generated at the output of the control unit 1: the contents of counter 2 are incremented. At the same time, the code of the interface command 0П0 is sent to the decoder 49. At the outputs of the decoder 49, the following voltages are generated: - the level "Log.1", on {5 others - the level "Log.O". By a positive differential from the output of element I 26 at the output of the former 31, a positive impulse is formed which, acting through elements 20 20 54 and 55 to the input of element I -NE 41, forms at the exit pic The local signal of the local communication message INB. At the same time, the signal from the output of element 41 is fed to the input of the element OR 36, at 25 the signal of the local message PRE is generated at the output of the latter. On the data bus of the CPC LD0-LD7, the interface command code 0П0 is issued.

The next interface command displayed by the memory is the MAI command, which contains the address of the device that is first polled by the controller. The command code MAI, acting on the input of the decoder 49 of the control unit. It sets the "Log.1" level on all its outputs. At the same time, at the output of the element IS-NOT 20, if the function K is in the state of SCC and the function P is in the SPAD state, then with the arrival of the SD signal, a negative impulse is formed, which sets the trigger 23 to one state and is output to the PNO output of the unit 1 management. Signal45 of the local message at the output of the NAND 33 element forms a negative differential that arrives at the ϋ-input of the shaper 37, while at its output a signal of the local communication 50 GTH is formed.

The device, addressed by the previous command of the MAI for transmission with the transition of the interface function K from the SSC state to the ACL state, sends the status byte of the LDO-LD7 CPC to $$.

The message "Service is prohibited, camping" (SCR) is sent on line LD6 simultaneously with the message of the BLS. If a

If the addressed device did not request LD6 service in the "Log.O" state, then the level of "Log.1" is not output by the AND-28 element and the state of the trigger 66 does not change. With the arrival of the DM signal, a negative impulse is generated at the output of the NAND 28 element, which is applied to the AND 53 element, and at the output of the element, a signal is generated from the local MAS message. At the same time, the leading edge of the LED signal, the trigger 23, is set to the zero state, while the “Log.1” level arrives from the zero output of the trigger 23 on the And 26 element. At the output of the element And 26 is formed a positive differential, which is fed to the C input of the trigger 32, and through the element AND NOT 39 on the direct-input.

Claims

Claim

A computer interface with a public channel, containing the control word register, status register, first, second input / output registers, decoder, receiver synchronization unit, transmitter synchronization unit, receiver, transmitter, synchronization unit, the first information input-output of the first input register -inputs, information <control-register word input and information output of the status register are the input-output of the device for connecting the computer data bus, the second information output of the first The I / O register is connected to the first information input-output of the second I / O register, the second information input · whose output is the input-output of the device for connecting the data bus of the common channel, the service request generation unit, the output of which is the output of the device for connecting to input interrupt computer, the first, second outputs of the control word register are connected respectively to the input of the transmitter and to the enable input of the synchronization unit, the first, second outputs of which, the first the output of the transmitter's synchronization block, the first output of the synchronization block of the receiver and the output of the transmitter are the outputs of the device for connecting, respectively, the local and remote control inputs 1591026 12

control, data synchronization input, readiness input and public transmission end input, it is different from the fact that, in order to reduce the cost of computer time when implementing the sequential polling function, a control unit, a counter, an operational storage unit, an address register, a transceiver are entered into it and a multiplexer of local messages, with the clock output, the load output, the reset output and the address output of the control unit are connected to the synchronization, load, reset and information inputs respectively counter whose output is connected to the address input of the random access memory unit, whose output is connected to the address input 20

the control unit, with the information input of the address register and with the first input-output of the transceiver, the second input-output of which is connected to the output of the address register and the first 25 information input-output of the second I / O register, the third to the fifth outputs of the control word register are connected respectively with a write input, with the first gate 39 input of the control unit and with the synchronization input of the address register, whose resolution input is connected to the service request input of the control unit and is the device input To connect the startup output to the service of the common channel, the interface reset inputs, the synchronization of data reception and synchronization of the control unit are the corresponding inputs of the device for connecting the outputs from the interface cast, synchronizing the reception of the common channel and the output of the device for connecting the data synchronization input the third channel, the third, fourth outputs of the synchronization unit are connected respectively to the initialization and standby inputs of the control unit, readiness outputs when memory, waiting, transfer of control, refusal to receive a local message and receive a local message of the control unit are connected respectively to the first to fifth informational inputs of the multi-type local messageer output, output, byte-by-sync control unit, connected to the address enable input and with the sixth information input of the local messages multiplexer, the write, sample, and transmission direction settings of the control unit are connected respectively to the read / write input of the operational storage unit and The first to sixth outputs of the decoder are connected to the sample and transmission directions of the transceiver, respectively, from the seventh to the twelfth information inputs of the local message multiplexer, the first to sixth outputs of which are connected respectively to the enable input of the transmitter synchronization unit, to the receiver set and reset inputs, c synchronization inputs of the synchronization block of the receiver synchronization block, with the synchronization block inhibit input and the synchronization block readiness input the output of the request of the control unit is connected to the input of the generation unit, the service request, the first to third status inputs and the information input of the control unit are connected respectively to the second outputs of the transmitter and receiver synchronization blocks, to the output of the receiver and to the second information input — the output of the second input register output, and the control unit contains the first through the fourth elements, NOT, the first through the twelfth elements AND-NOT, the first through the seventh pulse shapers, the first through sixth triggers, the first th to the tenth elements are AND, from the first to the sixth elements OR and the decoder, and the input of the first element is NOT the data synchronization input of the control unit, the output of the first element is NOT connected to the first input of the first AND-N element, the first input of the second AND-NOT element is the input The control unit's record, the output of the first element is NOT connected to the first input of the third element NAND, the first input of the first element I is the input of the record of the control unit, the first, second inputs of the second element I are respectively the input of initialization and n The first state input of the control unit, the output of the first element AND-NOT connected to the single input of the first. trigger and is the waiting output of the control unit, the synchronization input of the first trigger is the input of data synchronization of the control unit,

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the zero output of the first trigger is connected to the third input of the second element AND, the single output of the first trigger is connected to the second input of the third- $ of its element IS-NOT, the input of the decoder is the address input of the control unit, the first, second outputs of the decoder are connected to the first inputs of the first and second respectively elements OR, the output of the first element AND is connected to the first input of the fourth element NAND, the second, third inputs of which are respectively the information input and the waiting input 15 of the control unit, the output of the first element This AND is connected to the first input of the fifth element NAND, the second, the third inputs of which are respectively the initialization input and the second input 2E of the state of the control unit, the output of the first element I is connected to the fourth input of the second element AND, to the single input of the second trigger, s the third input of the third element 25 NAND and the second input of the first element NAND, the third, fourth inputs of which are connected respectively to the third output of the decoder and to the third input of the block state, the output of the second 50 element AND is connected to the synchronous input second trigger element and the input of the third element AND, the output of the first pulse shaper is connected to the second input of the second element ~ e5 and AND-NOT, the output of the second pulse shaper is connected to the first input of the third pulse shaper and is the load output of the control unit, the second input and output

The third pulse shaper is connected respectively to the output of the second NAND element and to the reset output of the control unit; the output of the third And element is connected to the first 45 input of the fourth pulse shaper, the output of which is connected to the first input of the sixth AND NAND element, the output of which is connected to zero input the third trigger, the unit input of which is connected to the output of the second element NOT, the output of the fourth pulse shaper through the third, fourth elements is NOT connected to the first inputs of the seventh and eighth elements AND-NOT , the zero output of the third trigger is connected to the second input of the eighth element NAND and the first input of the ninth element NAND, the second, third inputs of which are connected respectively to the output of the first element AND and to the input initialization of the block, the output of the fifth element is NOT connected to the input of the fifth pulse generator, the output of which is the readiness output of the block, the output of the ninth element AND-NOT connected to the first input of the sixth pulse shaper, the second input of which is the input of data synchronization of the block, the first, second input The third element OR is the recording input and the first gate input of the block, the output of the third element OR is connected to the first input of the tenth element NAND and is the write output of the control unit, the second input and output of the tenth element NAND are respectively connected to the output of the sixth pulse shaper and with a clock output of the control unit, the unit output of the third trigger is connected to the second input of the seventh IS-NOT element, the output of the eighth element IS-NOT is connected to the single input of the fourth trigger, with an output of one-byte synchronous control unit and with the second inputs of the first, second OR elements, the outputs of which are respectively the outputs of the failure to receive the local message and receive the local message of the control unit, the first input of the fourth element AND and the zero input of the fourth trigger are the recording entry of the block, the synchronization input of the fourth trigger is the data synchronization input of the control unit, the unit and zero outputs of the fourth trip-mer are connected respectively to the output of the transmission direction setting of the control unit and to the second in the fourth element And whose output is the output of the control unit selection, the single input and the synchronization input of the fifth trigger are the receive synchronization inputs and the first gate input of the control unit, respectively, the output of the seventh AND-NO element is connected to the first input of the fifth And element, the second input of which is the reset input of the interface of the control unit and is connected to the first input of the eleventh NAND element, the fourth output of the decoder is connected to the single input of the sixth trigger and to the first input of the sixth pole AND gate, a second input and an output koto15

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connected to the output of the third NAND element and to the control output of the control unit, the fifth one, the output of the decoder is connected to the zero input of the sixth trigger, the zero output of which is connected to the first input of the fourth pulse shaper and the second element AND connected to the second input of the fourth pulse shaper, the third input of which is connected to the output of the third element AND, the first input of the seventh pulse shaper, the first input of the fifth element OR, the first input of the seventh The second element And the information input of the second trigger is connected to the service request input of the control unit, the zero output of the seventh pulse shaper is connected to the first input of the eighth And element, the output of the fourth AND element is NOT connected to the first input of the ninth And element, the second input and output are connected respectively, with a single output and information, the input of the fifth trigger, the unit output of which is connected to the second input of the first element And, the unit output of the seventh pulse shaper is connected to the first input House fourth OR gate, whose output is connected to the input of the second pulse generator, the second input of the seventh pulse generator, a second input

the eleventh AND-NAND element and the first input of the tenth AND element are connected to the control unit recording input, the output of the fifth AND element is connected to the second input of the eighth AND element, to the first input of the twelfth AND-N element and to the second input of the tenth AND element, connected to the first input of the first pulse shaper, the second input of which is connected to the output of the sixth OR element, the first, second input of which is connected respectively * to the single output of the second trigger and to the output of the seventh And element, the second input of which union of a zero output of the fifth flip-flop output :, unit of the sixth flip-flop is connected to the fifth th input of the second AND gate, to the third inputs of the first and tenth AND gates e and fourth inputs of the fourth, fifth AND-NO elements, the zero output of the second flip-flop is connected. with the second input of the sixth element AND-NOT, the output of the eleventh element AND-NOT connected to the second input of the fifth element OR, the output of which is connected to the second input of the twelfth element AND-NOT, the output of which is connected to the second input of the fourth element OR, the output of the eighth element AND is information output of the control unit, a single output of the third trigger is connected to the second input of the seventh element I.

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