KR0174686B1 - Routing address generating methdo and circuit thereof for message communication among control systems in atm switching system - Google Patents

Abstract

In the present invention, an ATM switch uses a commercially available segment / reassembly circuit 103 for ATM cell segmentation to implement message communication between control systems using an ATM switch transmission path by adding 3 bytes of routing addresses 53 bytes before an ATM cell. The CPU 101 writes the message to be sent to the packet memory 107, and the CPU 101 writes the written area and size of the packet memory 107 of the message to be sent to the control memory 105. Let's do it. On the other hand, the CPU 101 determines the counterpart control system to be transmitted and then writes the corresponding routing address to the routing address and the ATM 1 cell transmitter 109, and the CPU 101 reads the segment / reassembler circuit 103. Let it be. The segment / reassembler circuit 103 applies the SS_CELAVL signal to the routing address and the ATM cell transmitter 109 that it is ready to transmit. At this time, the routing address and the ATM cell transmission unit 109 generate the routing address 3 bytes written by the CPU 101 together with the STRB signal through the TAXID [0: 7] to transmit to the transparent asynchronous transmission and reception interface unit 111. It is configured to be applied.

Description

Routing address generation method and circuit for message communication between control systems in ATM switching system

The present invention relates to a routing address generating circuit for finding a destination port in an ATM switching system. In particular, when a control system wants to send a message to another control system, it transmits a message in an ATM cell unit before each ATM cell. A routing address generating circuit and method for message communication in a switching system for attaching three bytes of routing addresses.

In general, TDX exchanges before the development of ATM-ESS exchanges have used HDLC protocols for message transfer between control systems. In other words, the message transmission between the control systems used a dedicated IPC transmission channel completely separate from the voice data. To this end, conventionally, commercially available HDLC controllers MC-68561 and MC-68562, which provide HDLC photo call functions, were mainly used. In the IPC buses between the control systems, a round robin type H / W is used, and the control systems share the IPC buses with each other. The use of such a bus allows a counter to be built into each control system so that it can be used for a certain time defined by the counter. For example, if one control system occupies the IPC bus and generates a maximum of 220 bytes of messages, all other control systems receive it. In the HDLC protocol, the message head part receives the entire message only when it matches the unique IPC address of each control system. However, in the conventional TDX exchange, the message communication between the control systems uses the HDLC transmission method through an IPC-only transmission path, but the message communication between the control systems of the ATM-ESS exchange uses an ATM switch, so it must be adapted to the ATM cell transmission method. Therefore, the existing HDLC matching logic cannot be accommodated in an ATM switch. Therefore, a function for matching an ATM switch is required, and a routing address 3 byte generating means is required.

Accordingly, an object of the present invention is to provide a method and circuit for implementing message communication between control systems using an ATM switch transmission path by adding 3 bytes of routing addresses in front of 53 bytes of an ATM cell.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to an embodiment of the present invention,

A control memory 105 which stores bus adjustment control data for message communication and program control data for synchronous / asynchronous interfacing;

A packet memory 107 which is accessed by the control of the central processing unit 101 and stores packet data;

Control to write a message to be transmitted to the packet memory 107, control to write the area and size written to the packet memory 107 to the control memory 105 for the message to be transmitted, and to transmit the message. A central processing unit (101) for determining a counterpart side control system and controlling routing addressing corresponding thereto;

A segment and reassembler (SARA) circuit 103, which is enabled by the control of the central processing unit 101, makes the general transmission packet data into the ATM format data or the ATM format data into the general data. ,

A read control signal is supplied to a lead enable end SS-RDEN of the segment / reassembler circuit 103 by a signal of a cell valid signal terminal CELAVL generated by the segment / reassembler circuit 103. The segment / reassembler circuit 103 is a signal that may read data and generates a command TXCMD and a strobe signal STRB indicating that there is data to be transferred to the next stage, but after the SS_RDEN signal is generated, Routing address for ATM 1 cell start / stop command, 3-byte routing address, and ATM 1 cell 53 bytes from the routing address written by the CPU 101 after receiving the data according to clock 53 after the second clock. A cell data transmission unit 109,

The routing address and the signal of the strobe terminal (STRB) generated by the ATM 1 cell data transmission unit 109 recognize that the data of the command (TXCMD) and data bus (TAXID) are valid, but not to the command (TXCMD). It consists of a transparent asynchronous transmission and reception interface unit 111 which transmits 3 bytes from the start of transmission of ATM 1 cell to the routing address and transmits the cell data from 4 bytes to 56 bytes and then completes the transmission according to the ATM 1 cell completion command. do.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIG.

The ATM exchange uses segment / reassembly circuit 103, a commercial chip, for ATM cell segmentation. In Fig. 1, the CPU 101 writes a message to be sent to the packet memory 107, and the CPU 101 controls the written area and size of the packet memory 107 of the message to be sent. Light). On the other hand, the CPU 101 determines the counterpart control system to be transmitted, and then writes the corresponding routing address to the routing address and the ATM 1 cell transmitter 109, and the CPU 101 checks the segment / reassembler circuit 103. Let it be.

The segment / reassembler circuit 103 applies the SS_CELAVL signal to the routing address and the ATM cell transmitter 109 that it is ready to transmit. At this time, the routing address and the ATM cell transmission unit 109 generate the routing address 3 bytes written by the CPU 101 together with the STRB signal through the TAXID [0: 7] to transmit to the transparent asynchronous transmission / reception interface unit 111. Is authorized. The segment / reassembler circuit 103 receives the SS_RDEN generated from the routing address and the ATM cell transmitter 109 immediately after the SS_CELAVL signal is input, that is, just before the fourth clock. After the fifth clock, SS_FFD [0: 7] is output in accordance with the clock 53 times, together with the STRB signal. Therefore, 3 bytes of routing address and 53 bytes of ATM cell are transmitted to the switch.

The process until the ATM 1 cell is transmitted is as follows.

Tx Start Command + Routing Address (Routing Address 3Bytes) + ATM 1 Cell (53Bytes) + Tx End Command

The ATM 1 cell transmission start command and the transmission last command generated by the routing address and the ATM 1 cell transmitter 109 are generated by the TXCMD [3..0] bus, and the routing address -3 bytes and ATM 1 Cell (53 bytes). Is generated by the TDXID [7..0] bus. The STRB generated by the routing address and the ATM 1-cell transmission unit 109 indicates that a valid command (TXCMD [3..0]) or data (TAXID [7..0]) is input to the transparent transmission / reception interface unit 111. When the strobe signal is provided to the transparent asynchronous transmission and reception interface unit 111 through the strobe terminal STRB, 12.5 MHZ of the input clock terminal MCLK should always be generated for synchronization. And it should be synchronized to 12.5MHZ every clock from transmission start command to last command.

The CPU 101 controls the contents of the message to be transmitted, writes them to the packet memories 105 and 107, and then corresponds to the destination address of the switch corresponding to the routing address and the counterpart control system to be sent to the ATM1 cell transmitter 109. Write the routing address to be used. The data array is as follows.

LD31-24 23-16 15-8 7-0c Routing address First byte Second Byte Third Byte Don't care

FIG. 2 is a detailed circuit diagram of the routing address and ATM 1 cell transmitter 109 of FIG.

Data (LD) 31..8 provided from the CPU 101 is controlled by the clock stage CLK generated by the address strobe LAS and the write control signal LWR from the output of the OR gate OR1. A deflip-flop DF1 for generating a routing address signal (RAAD) 31..8;

Clearing by the cell transmission completion signal (SS-CELAVL) generated from the segment / reassembler circuit 103 and selecting the transmission start / end command, routing address, and ATM 1 cell data according to the signal of the strobe end (STRB). A flip-flop (DF1) for generating a reference signal for

And-agate (AN1) for generating a strobe (STRB) to be provided to the transparent asynchronous transmission and reception interface unit 111 by inverting in the inverter (N1) for the absence of the cell transmission completion signal (SS-CELAVL),

A first comparator (COP1) generating 10 as a transmission start command when the fixed end 0 is equal when the output of the flip-flop DF2 is 0,

When the output of the flip-flop DF2 is 1 to 3, the fixed stages 1 to 3 are compared sequentially, and if the same is the same, it is generated by sequentially selecting the routing address RAAD generated by the first flip-flop DF1. 2-4 comparator (COP2-COP4),

When the output of the flip-flop DF2 is 4 to 56, the fixed stages 4 to 56 are sequentially compared, and if the same, the ATM 1 cell data (SS-FFD) generated by the segment / reassembler circuit 103 is selected and read. A fifth comparator CO5 generating the enable signal SS_RDEN;

When the output of the flip-flop DF2 is 57, the fixed end 57 includes a sixth comparator CO6 that generates 1 as a transmission end command.

As described above, TXCMD [3..0] = 0010 in the routing address and the ATM 1 cell transmitter 109 indicates that the transparent transmit / receive interface unit of the counterpart control system receives when the transparent transmit / receive interface unit 111 encodes and sends it to TXD. 111, RXCMD [3..0] 0010, and the receive control logic knows that a receive (Tx) operation is started.

The routing address bytes written in the internal address, which is the flip-flop DF1 of the routing address and the ATM 1-cell transmission unit 109, are stored within 3 clocks of TDXID [1] from the first byte in the second-4 comparators COP2-COP4. 7..0]. At this time, of course, the transparent asynchronous transmission / reception interface unit 111 notifies that the valid TAX [7..0] is input to the STRB generated by the fifth comparator CO5. When the last third byte is generated as TAXID [7..0], SS_REDEN is provided to the segment / reassembler circuit 103 by the fifth comparator CO5 of the routing address and the ATM 1 cell transmitter 109. In the fourth clock after the transfer start command, the segment / reassembler circuit 103 starts to transmit data read from the control and packet memories 105 and 107 to SS_FFD [7..0] by byte. At this time, the routing address and the ATM 1 cell transmitter 109 transmits the SS_FFD [7..0] input during the 4-56 clocks after the transmission start command to the TAXID [7..0]. This means that the actual ATM 1 cell has been transmitted, and a transmission end command is generated in the sixth comparator C06 to indicate the end of the transmission.

Tx End Command is defined as TXCMD [3..0] = 0001

Specific implementation of the routing address and transmission unit 103 is as follows.

% [1] Routing Address 3bytes store from CPU%

iradd []. clk = iadlatch;

iradd []. d = id [];

radd [] = iradd []. q;

adlatch =! las! lwr;

% [2] Counter for cell transfer%

itq.clk =! strb;

itq.clrn =! ss_celavl;

tq [] = itq. (qh, qg, qf, qe, qd, qc, qb, qa);

% [3] SS_RDEN generation to SARA-S%

iftq [5..0] = 4 and tq [5..0] = 58then

ss_rden = vcc;

% [4] Tx Start Command (0010) generation to TAXI-TX%

iftxing == vcc and tq [5..0] == 0 then

txcmd [] = B10;

% [5] Tx End Command (0001) generation to TAXI-TX%

else iftq [5..0] == then

txcmd [] = B1;

% [6] STRB generation to TAXI-TX%

strb ==! 112.5mclk txing.q;

% [7] Routing Address 3bytes generation to TX taxi%

if tq [5..0] == 1 then

taxid [] = radd [31..24];

else if tq [5..0] == 2 then

taxid [] = radd [23..16];

else if tq [5..0] == 3 then

taxid [] = radd [15..8];

else

taxiout [] = ss_ffd [];

1 is a circuit diagram according to the present invention

FIG. 2 is a detailed circuit diagram of the routing address generator 109 of FIG.

No content.

As described above, by designing a register using a part of the coordinator used in H / W development, a routing address 3-byte generation circuit can be implemented. It can be applied to the circuit inexpensively by adding an easy-to-use FIFO, which makes it difficult to control peripheral FIFOs and eliminates transmission delays and error-prone sections. In addition, S / W intervention is not required for generating 3 bytes of routing addresses in every ATM cell. This is because the contents of the routing address in the register are always generated before updating to the implemented register. First of all, this implementation has the advantage of enabling message communication between control systems in a small ATM-ESS exchange that is currently being jointly developed.

Claims (2)

In a message communication system in an exchange system, A control memory 105 which stores bus adjustment control data for message communication and program control data for synchronous / asynchronous interfacing; A packet memory 107 which is accessed by the control of the central processing unit 101 and stores packet data; Control to write a message to be transmitted to the packet memory 107, and control to write an area and size written to the packet memory 107 to the control memory 105 for the message to be transmitted, A central processing unit (101) for determining a counterpart side control system and controlling routing addressing corresponding thereto; A segment / reassembler circuit 103 which is enabled by the control of the central processing unit 101 and generates general transmission packet data into ATM format data or ATM data of 7 data into general data; A read control signal is supplied to a lead enable end SS-RDEN of the segment / reassembler circuit 103 by a signal of a cell valid signal terminal CELAVL generated by the segment / reassembler circuit 103. The segment / reassembler circuit 103 provides a signal indicating that data may be read, and generates a command TXCMD and a strobe signal STRB indicating that there is data to be transferred to the next stage, and after the SS_RDEN signal is generated, Routing address and ATM 1 that receive data according to the 53rd clock after the first clock and generate ATM 1 cell start / stop command, 3-byte routing address and 53 bytes of ATM 1 cell from the routing address written by the CPU 101. A cell data transmission unit 109, The routing address and the signal of the strobe terminal (STRB) generated by the ATM 1 cell data transmission unit 109 recognize that the data of the command (TXCMD) and data bus (TAXID) are valid, but not to the command (TXCMD). It consists of a transparent asynchronous transmission and reception interface unit 111 which transmits 3 bytes from the start of transmission of ATM 1 cell to the routing address and transmits the cell data from 4 bytes to 56 bytes and then completes the transmission according to the ATM 1 cell completion command. Circuit characterized in that. According to claim 1, Routing address and ATM 1 cell data transmission unit 109 Data (LD) 31..8 provided in 101 is controlled by the clock stage CLK generated from the address strobe LAS and the write control signal LWR from the output of the OR gate OR1. A deflip-flop DF1 for generating a routing address signal (RAAD) 31..8; Clearing by the cell transmission completion signal SS-CELAVL generated from the segment / reassembler circuit 103, and selecting the transmission start / end command, routing address, and ATM 1 cell data according to the signal of the strobe end STRB. A flip-flop (DF1) for generating a reference signal for And-agate (AN1) for generating a strobe (STRB) to be provided to the transparent asynchronous transmission and reception interface unit 111 by inverting in the inverter (N1) when there is no cell transmission completion signal (SS-CELAVL), A first comparator (COP1) generating 10 as a transmission start command when the fixed end 0 is equal when the output of the flip-flop DF2 is 0, When the output of the flip-flop DF2 is 1 to 3, the fixed stages 1 to 3 are compared sequentially, and if the same is the same, it is generated by sequentially selecting the routing address RAAD generated by the first flip-flop DF1. 2-4 comparator (COP2-COP4), When the output of the flip-flop DF2 is 4 to 56, the fixed stages 4 to 56 are sequentially compared, and if the same, the ATM 1 cell data (SS-FFD) generated by the segment / reassembler circuit 103 is selected and read. A fifth comparator CO5 generating the enable signal SS_RDEN; When the output of the flip-flop (DF2) is 57, the fixed end 57, the sixth comparator (COP6) for generating a 1 as a transmission end command circuit, characterized in that