KR100369403B1 - Host interface apparatus for processing AAL and method thereof - Google Patents

Abstract

The present invention relates to a host interface device for AAL processing and a control method thereof. The present invention relates to a function of receiving a transmission data transmission request of an AAL, reading from an area of the host memory 110, and delivering the received data to the AAL. Message queue for queuing the transmission request message 131 of the host and the transmission completion message from the AAL processing unit 140 to the host interface unit 130 which converts the write and read signals to be transmitted according to internal operations. Put 132; Managed by the AAL processing unit 140, the AAL processing unit 140 reads the transmission request message 131 from the host interface unit 130 and allocates a buffer descriptor index from the descriptor pool 151 to the host memory 110. The link is allocated after the buffer is allocated, and the buffer descriptor pool 151 registers the buffer descriptor index as the descriptor pool 151 when transmission is completed.

Description

Host interface apparatus for processing AAL and its control method

The present invention relates to an interface between an ATM Adaptation Layer (hereinafter, abbreviated as "AAL") used for a user interface of an ATM (Asynchronous Transfer Mode) network and a host module for controlling the same. Simplified in terms of bus, the present invention relates to a host interface device for AAL processing to eliminate unnecessary occupancy of the host bus.

In general, ATM communication is divided into vertical structures such as physical layer, ATM layer, AAL, and higher protocol layer. The AAL is divided into a truncation and recombination sublayer and a converging sublayer, and the physical layer is a physical medium and a transmission convergence layer. It is divided into sublayers.

As described above, the ATM related technology is described in US Patent Nos. 5,548,587, "Asynchronous Transfer Mode Adapter for Desktop Applications" and 5,768,275, "Controller for ATM Segmentation and Reassembly," to date, to improve the efficiency of ATM and AAL processing on the user side. It is processed in hardware. Details are as follows.

As shown in FIGS. 1 and 2, elements for implementing an interface between an AAL processing unit used for a user network interface (UN) of an ATM network and a host module controlling the same may include a host memory 10 and a host processor. 20), the host interface 30, the AAL processing unit 40, and the local memory 50.

The host memory 10 stores data for making a transmission request when data to be transmitted is generated.

The host processor 20 manages data of the host memory 10, and functions to request and partially control transmission by writing and reading the AAL processor 40 and the local memory 50.

The host interface 30 functions as two functions, a function of converting a write and read signal of a host bus according to internal operation (SLAVE function: 32) and a request for transfer of transmission data from an AAL processor. A function (DMA function or master function 31) is read from the memory 10 and transferred to the AAL processing unit 40.

The AAL processor 40 determines a transmission channel by referring to a register value set by a host and tables in a local memory, and performs a protocol layer function related to transmission.

The local memory 50 stores a series of variables and tables used for hierarchical processing in the AAL processor 40. The local memory 50 includes a transmission request queue 51, a transmission completion queue 52, and settings for each channel. It consists of a channel table 54 and buffer descriptors 53 that describe one-to-one to the host's buffer.

At this time, the transmission request queue 51 and the transmission completion queue 52 of the local memory 50 and the transmission request queue read pointer register 41 and the transmission request queue write pointer on the AAL processing unit 40 in order to function as a queue. The register 43, the transmission completion queue read pointer register 42, and the transmission completion queue write pointer register 44 operate.

As shown in FIG. 3 in the above configuration, when transmission request data is generated in the host's memory (S1), the host reads a read pointer of the transmission completion queue 52, and the host transmits a transmission completion queue 52. Increment the read pointer (S2).

The host describes contents related to the corresponding buffer descriptor buffer in the local memory 50. The contents described here include the buffer start address, the buffer length, the channel number, the data information in the buffer, and the like.

However, in the conventional method of requesting a transmission, since the transmission completion queue and the transmission request queue are used, they need to manage their read write pointers and read write pointer registers, and read registers and write local memory through the host bus. Since the host bus cannot use the transmit data, there is a problem that the efficiency of the host bus is lowered during the DMA operation of the transmit data.

In this case, when the unit of data requested to be sent to the host memory is large, the effect of such degradation is not so large. However, when the data unit of the host memory is small, such as the recently standardized AAL2 application, when a frequent request is made to the host memory. Considering this, the impact on the efficiency of the host bus is so great that the problem becomes even greater.

Accordingly, the present invention has been made in view of the above problems, and reduces access of a host bus when a request for transmitting data is transmitted through the host bus in an interface between an AAL layer used for UNI of an ATM network and a host module controlling the same. The purpose is to provide a high speed host interface by eliminating unnecessary occupancy of the host bus.

1 is a transmission block diagram of an ATM and an AAL according to the prior art;

FIG. 2 is a detailed block diagram of the data structure of the host interface and local memory of FIG. 1 according to the prior art; FIG.

3 is a flowchart illustrating transmission and reception between an AAL and a host interface according to the prior art;

4 is a schematic diagram of transmission and reception between an AAL and a host interface according to the present invention;

5 is a block diagram of transmission and reception between an AAL and a host interface in the present invention.

6 is a flowchart illustrating transmission and reception between an AAL and a host interface in the present invention.

Explanation of symbols on the main parts of the drawings

110: host memory 120: host processor

130: host interface 131: transmission request message

132: message queue 140: AAL processing unit

141: buffer descriptor link function 142: register

142 ': descriptor pool read pointer register

142 ": descriptor pool write pointer register

150: local memory 151: descriptor pool

152: buffer descriptor 153: channel table

In order to achieve the above object, the present invention manages a pair with a table corresponding to the data block of the host memory in the local memory used by the AAL layer when the host delivers data to be transmitted to the AAL layer. When a data block occurs in a data block in the host memory, the index of this table entry is registered in the send request queue to close the send request, and the host registers it in the waiting queue that has been sent so that the host can reuse it. There is a feature configured to reduce the cycle of checking the queue.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic diagram of an interface structure according to an embodiment of the present invention, and FIG. 5 is a block diagram of transmission and reception between an AAL and a host interface of the present invention.

As shown in FIG. 4 and FIG. 5, the present invention provides a host memory 110 for storing data to be transmitted, a host for requesting transmission of data to be transmitted, controlling an AAL processing unit in connection with transmission, and initializing a local memory. The processor 120 receives the transmission data transmission request of the AAL, reads from the area of the host memory 110, transfers the data to the AAL, and writes and reads signals transmitted by the host through the host bus to fit the internal operation. Reads the queue transmission request message 131 from the function of converting and the transmission request message 131 of the host and the transmission completion message from the AAL processing unit 140, allocates the corresponding buffer descriptor 152, and allocates the allocated buffer descriptor 152. By the AAL processing unit 140 for linking to the channel and the transmission order list, the parameters used by the AAL processing unit 140 in the transmission operation, and the host. It comprises a channel table is initialized 153 and the buffer descriptor 152 and the descriptor pool local memory 150 to 151 is located.

The descriptor pool 151 is managed by the AAL processor 140, and the AAL processor 140 reads the transmission request message 131 from the host interface 130 and allocates a buffer descriptor index from the descriptor pool 151. The link is allocated after the buffer of the host memory 110 is allocated, and when the transmission is completed, the buffer descriptor index is registered in the descriptor pool 151.

Referring to Figure 6 the operation of the present invention configured as described above in detail as follows.

First, the host generates transmission request data in the host memory 110 in order to send the data block to be transmitted in sequence (S11), and the host transmits a request message (buffer start address, buffer length, channel information, Buffer number and the like) are registered in the message queue 132 of the host interface unit 130. Registration with the message queue 132 is written like a general register write (S12).

The read and write pointers of the message queue 132 are managed in the host interface.

At this time, the transmission request registered in the message queue 132 of the host interface unit 130 is read by the AAL processing unit 140, the descriptor index is read from the descriptor pool 151 of the local memory 150, and the descriptor is transmitted to the requested buffer. Assigns to contain the contents of the transmission request message read from the host interface unit 130 (S13).

In the descriptor allocated in S13, a field containing a buffer number is provided, and when the transmission of the data of the corresponding buffer descriptor is completed, the buffer number is transferred to the host by the completion message of the host interface to the host (S14).

Therefore, the host reads the buffer number of the completion message and fills the buffer again with new data.

The present invention is not limited to the above-described specific preferred embodiments, and various modifications can be made by those skilled in the art without departing from the gist of the present invention described in the claims. Of course, such a change is of course within the scope of the present invention.

As described above, the present invention reduces the access of the host bus when requesting transmission of transmission data through the host bus, so that the host bus can be spared so that the generated data of the host when the transmission of the transmission data from the host bus is carried out. It can deliver data close to its maximum speed, so it can process data at high speeds, making it very effective in designing hardware for high-speed network interfaces.

Therefore, the present invention is very useful for designing a high speed host interface since the number of times of access of the host bus is reduced by changing the transmission request structure for accessing the host bus in a conventional manner when a transmission request is made.

Claims (3)

A host memory (110) and a host processor (130) for registering a transmission request message in a message queue (132) of the host interface unit (130); An AAL processing unit 140 for storing the content of a request message of the message queue 132 in a descriptor of an index read from the descriptor pool 151 of the local memory 150; And a buffer descriptor (141) configured to include a buffer number in a transmission completion message and deliver the buffer number to the host when the data transmission of the corresponding buffer is completed after the field containing the buffer number is completed. delete The host using the host bus to write a transmit request message (buffer start address, buffer length, channel information, buffer number, etc.) to a register; And the AAL processing unit reads the transmission request data, reads the descriptor index from the descriptor pool, and allocates the descriptor to the transmission request buffer.