KR19990074741A - Asynchronous transmission mode cell transmission apparatus and method of asynchronous transmission mode adaptation layer type 5 - Google Patents

Abstract

The present invention relates to an asynchronous transmission mode (ATM) cell transmission apparatus of an asynchronous transmission mode adaptation layer type 5, wherein packet data for transmission is stored in internal packet buffers, and the host 30 reads the requested packet buffer. A host 30 for transmitting data in the host, a local memory 60 in which information on the packet buffers of the host 30 are stored, and a plurality of rate queues are stored, and the rate queues are stored up to a specified count value. A rate queue logic circuit 70 for counting a clock and outputting a transmission request signal, wherein the link control circuit 10 uses information stored in the local memory 60 to transmit at a transmission rate corresponding to the rate queue. The packet buffers are linked to each other by the rate queue and the transmission channel, and the overall control circuit 20 outputs the transmission request signal when the transmission request signal is applied. With respect to the packet buffer with a different transmission channel of the linked packet buffer corresponding to the read request in order to walk, the erasure from the link with respect to the packet buffer read out is completed.

Description

Asynchronous transmission mode cell transmission apparatus and method of asynchronous transmission mode adaptation layer type 5

The present invention relates to an asynchronous transfer mode (ATM), and more particularly, an ATM cell transmission apparatus of an asynchronous transfer mode adaptation layer type 5 (hereinafter referred to as AAL type 5). And to a method.

ATM networks have standard protocols separated into three layers: the physical layer, the ATM layer, and the AAL. That is, packet data for transmission is first divided into 48 bytes in the AAL layer, and at the ATM layer, a 5-byte header including destination information of the other party is added to form a 53-byte cell which is a basic data unit of ATM. In addition, the physical layer transmits an ATM cell from the ATM layer through a transmission path.

The AAL layer, on the other hand, is a layer that matches and adjusts data units (variable length of 1 byte for voice and variable length up to several kilobytes for data) and 48-byte user information uniformly handled in a cell. to be. While the ATM layer does not depend on applications such as voice, video, and data, the AAL relies on higher level applications.

The services that can be provided by AAL can be classified into class A, B, C, and D according to the characteristics of upper layer application traffic.AAL type 1, AAL type 2, AAL type 3, and AAL type 4 to realize these services. The five protocols, AAL Type 5, are being reviewed.

1 is a conceptual diagram of a transmitter for transmitting an ATM cell through AAL type 5.

As shown, data to be transmitted in various upper layers includes common part convergence sublayer (hereinafter referred to as CPCS) (C1-Cn) of AAL type 5 (1) and cell division and assembly sublayer ( Segmentation and Reassembly Sublayer (hereinafter referred to as SAR) (S1-Sn) is formed into a cell form and transmitted to the ATM layer 2 for each channel. The ATM layer 2 selects and outputs cells from the AAL type 5 (1) corresponding to the transmission rate (rate) assigned for each channel through the internal multiplexer MUX1, and the ATM header adding unit HG1 outputs the multiplexer. After adding necessary channel information to the cells of the MUX1, the configuration is applied to the physical layer.

On the other hand, as described above, although the concept of a transmitter for transmitting an ATM cell through AAL type 5 is established, a detailed hardware configuration has not been proposed, and CPCS and SAR functions are simultaneously performed in the AAL type 5 layer. In doing so, there was a problem that the configuration was complicated.

The present invention has been made in view of the above situation, and an object of the present invention is to provide an ATM cell transmission apparatus of AAL 5 that enables the transmission of an ATM cell through AAL type 5.

Another object of the present invention is to provide an AAL type 5 ATM cell transmission method that enables the transmission of an ATM cell through AAL type 5.

1 is a conceptual diagram of an asynchronous transmission mode cell transmission device of the asynchronous transmission mode adaptation layer type 5;

2 is a block diagram of an asynchronous transmission mode cell transmission device of the asynchronous transmission mode adaptation layer type 5 according to the present invention;

3 is a block diagram of a local memory configured in the asynchronous transmission mode cell transmission apparatus of the asynchronous transmission mode adaptation layer type 5 according to the present invention;

4 is a diagram illustrating a format state of a descriptor configured in a local memory in an asynchronous transmission mode cell transmission device of the asynchronous transmission mode adaptation layer type 5 according to the present invention;

5 is a diagram illustrating a format state of a virtual channel table configured in a local memory in an asynchronous transmission mode cell transmission device of the asynchronous transmission mode adaptation layer type 5 according to the present invention;

6 is a flowchart illustrating a method in which a link control circuit forms a link to descriptors in the asynchronous transmission mode cell transmission apparatus of the asynchronous transmission mode adaptation layer type 5 according to the present invention;

7 illustrates a state of a descriptor link formed according to the flowchart of FIG. 6;

8 illustrates a method of forming and transmitting an asynchronous transmission mode cell in the order of a descriptor link formed in the asynchronous control mode cell transmission apparatus of the asynchronous transmission mode adaptation layer type 5 according to the present invention as shown in FIG. Flowchart.

<Description of the symbols for the main parts of the drawings>

10 link control circuit 20 overall control circuit

30 host 40 host access control circuit

50: register circuit 60: local memory

70: rate cue logic circuit 80: memory access control circuit

90: packet data conversion circuit 110: cell buffer circuit

120: CS / ATM circuit 130: physical layer interface circuit

In order to achieve the above object, the present invention provides an ATM cell transmission apparatus of an asynchronous transmission mode adaptation layer type 5, in which data for transmission are stored in internal packet buffers, and a host transmitting data in a read buffer packet buffer. Wow; A local memory in which information about packet buffers of the host is stored; A plurality of rate queues are stored, the rate queues comprising: a rate queue logic circuit for counting an internal clock to a predetermined count value and outputting a transmission request signal; A link control circuit for mutually linking packet buffers for transmission at a transmission rate corresponding to the rate queue using information stored in the local memory for each rate queue and transmission channel; When the transmission request signal is applied, a read request is sequentially made to packet buffers having different transmission channels among the packet buffers linked corresponding to the rate queue that outputs the transmission request signal, and to the read packet buffers. A total control circuit for erasing from the link; A cell buffer circuit for assembling and outputting packet data from the host in units of cells; A CS / ATM circuit which inputs data from the cell buffer circuit and performs processing on the common part convergence sub-layer and the ATM layer on the input data; And a physical layer interface circuit for processing and transmitting the output of the CS / ATM circuit to match the input of the physical layer.

The present invention also provides an address area, a next horizontal descriptor area (NHD), and a next vertical descriptor area (NVD) area of a packet buffer in a host where data to be transmitted in a local memory is stored. Descriptors having the s, the virtual channel to which the packet buffer is to be transmitted and the virtual channel tables that store the corresponding rate queue, and the ready queues that store the addresses of the descriptors are stored, A rate queue having a method of linking descriptors in the local memory according to a transmission time point in an ATM cell transmission device of an asynchronous transmission mode adaptation layer type 5 assigned an address of a different starting descriptor, wherein the descriptors in the preparation queue are read. Shipping first descriptor Output step; A second descriptor reading step of reading a virtual channel table corresponding to a virtual channel table address stored in the read descriptor and reading an address of a start descriptor assigned to the rate queue stored in the virtual channel table; Determining whether the virtual channel addresses of the descriptors read in the first and second descriptor reads are the same; If the virtual channel addresses of the descriptors read in the first and second descriptor reading steps are the same, the descriptors stored in the NHD of the descriptor are sequentially read from the descriptor allocated to the rate queue, and the address of the descriptor is stored in the NHD. A first descriptor address storing step of storing an address of a descriptor read in the first descriptor reading step in a descriptor not written; If the virtual channel addresses of the descriptors read in the first and second descriptor read step are different, the descriptors stored in the NVD of the descriptor are sequentially read from the descriptor allocated to the rate queue, and the descriptor address is stored in the NVD. And a second descriptor address storing step of storing an address of the descriptor read in the first descriptor reading step in a descriptor not provided.

The present invention also relates to an adjacent horizontal descriptor area (NHD) in which an address of a packet buffer in a host, an identical rate queue, and an address of a descriptor assigned to the same channel are stored in which data to be transmitted is stored in a local memory. And descriptors having a Next Vertical Descriptor Address (NVD) area in which addresses of descriptors allocated with the same rate queue and different channels are stored, a virtual channel to which the packet buffer is to be transmitted, and a corresponding rate queue are stored. Virtual channel tables and rate queues having different transmission time points are linked through the NHD and NVD in an ATM cell transmission apparatus of an asynchronous transmission mode adaptation layer type 5, each assigned an address of a different start descriptor. The packet server using a descriptor A method is for reading in the data to the ATM selhwa, and the transmission request determining step of determining whether a transfer request from one of the queues rate; A data transfer request step of requesting the host for data transfer of a packet buffer corresponding to an address stored in a start descriptor corresponding to the rate queue, if there is a transfer request from the rate queue; ATM cellization by adding a header and a trailer to the packet data transmitted from the host to ATM cellization, and transmitting the same to a physical transmission medium; A descriptor erasing step of erasing from the local memory a link of the descriptor specifying the address of the packet buffer in which the data transfer is completed; An NVD determining step of determining whether an address exists in the NVD of the descriptor for which the transfer is completed; If an address exists in the NVD, a feedback step of reading a descriptor of the address and returning to the data transfer request step is provided.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic block diagram of an ATM cell transmission apparatus of AAL 5 according to the present invention, wherein the apparatus of the present invention transfers packet data of the host 30 by the link control circuit 10 and the overall control circuit 20 to the ATM cell. Will be sent as

That is, the host 30 forms a packet buffer on the internal memory and stores packet data to be transmitted in AAL type 5 in the packet buffer, and the link control circuit 10 stores the packet stored in the packet buffer of the host 30. A link according to a transmission channel and a transmission speed at which data should be transmitted is configured, and the overall control circuit 20 reads packet data from a packet buffer in the host 30 corresponding to this link to form an ATM cell and transmits the same. Do the process.

This configuration is described in detail as follows.

The host access control circuit 40 is connected to the host 30 and is configured to store and read data in the register circuit 50 and the local memory 60 under the control of the host 30. That is, the host access control circuit 40 is connected to the host 30 through a host address bus, a host data bus, and a host data control bus, and registers corresponding to the address signal according to a control signal applied from the host 30. The data of the data bus is written to a predetermined address of the circuit 50 and the local memory 60 or the data of the predetermined address is read and applied to the host 30.

Here, the data of the host 30 stored in the local memory 60 through the host access control circuit 40 become the start address, length, and related information of the packet buffer on the host memory in which the packet data are stored.

Meanwhile, the local memory 60 in which data of the host 30 is stored includes four blocks (descriptor table area, virtual channel table area, ready queue area, and the like) as shown in FIG. It is composed of a complete queue area, which is divided into a descriptor table base address, a virtual channel table base address, and a queue base address.

Here, a plurality of descriptors Des 1-Des n are stored for each address in the descriptor table area, and a plurality of virtual channel tables VCT 1-VCT n are stored for each address in the virtual channel table area.

In addition, addresses of descriptors Des 1-Des n are stored in the preparation queue area, and descriptors Des 1-Des n in this preparation queue area mean descriptors for which transmission is required as described below. In addition, the addresses of the descriptors Des 1-Des n are stored in the completion queue area, and the descriptors Des 1-Des n in the completion queue area are requested descriptors as described later. Means.

4 and 5 illustrate the formats of the descriptors Des 1-Des n and the virtual channel table VCT 1-VCT n.

FIG. 4 is a diagram illustrating a descriptor format. In the descriptors Des 1-Des n, a packet buffer length indicating a start address of a packet buffer in which packet data is stored, a packet buffer length to be transmitted, and a CPCS-PDU ( Protocol Data Unit) includes a cumulative length indicating the data length and a descriptor mode. Here, the descriptor mode includes bits used for cell transmission, and includes a bit indicating whether the packet is the last packet of the CPCS-PDU and the PTI value included in the cell header. In addition, the descriptors Des 1-Des n may include adjacent vertical descriptor addresses (Next Vertical Descriptor Address (NVD), horizontal descriptor addresses (NHD), read byte length, and virtual channel table address (VCT). One of 1- VCT n) is included. Here, the information in the above-described packet buffer start address, packet buffer length, cumulative length, descriptor mode and virtual channel table address are stored in the local memory 60 through the host access control circuit 40 as described above. ), NVD and NHD are stored under the control of the link control circuit 10 described above, and read byte length information is information stored under the control of the overall control circuit 20.

The NVD stored by the link control circuit 10 is assigned a same rate queue in the rate queue logic circuit 70 among a plurality of descriptors Des 1-Des n as described below, but having a different virtual channel Des. 1-Des n), where NHD is the same rate queue in the rate queue logic circuit 70 among a plurality of descriptors Des 1-Des n, and a descriptor having the same virtual channel (Des 1-Des). n). This will be described later in detail.

FIG. 5 shows the format of the virtual channel table VCT 1-VCT n, when ATM cells packetize the packets stored in the buffer of the host 30 in the virtual channel table VCT 1-VCT n and transmitted on a predetermined channel. A predetermined number of rate queues are formed in the required ATM cell header information area, the rate queue logic circuit 70 described later (rate queue logic circuit 70), and these rate queues are described below. Likewise, when one clock is counted with a different count value and the set count value is reached, a cell transmission request signal is output.) A count value area, a set value area, and a CRC that determine which cycle a service is to be performed. Result value storage area (because CRC is calculated for all data of CPCS-PDU, partial CRC data is calculated and stored every time a cell is transmitted). The header addition notification area RCell indicating whether the data is transmitted by adding the header or whether the data is transmitted as received from the host without the header, and the transmission rate of the corresponding channel belongs to which rate queue of the rate queue logic circuit 70. A rate queue number area, a start descriptor number, and an end descriptor number area indicating a message.

Here, the start descriptor number and the end descriptor number area are stored under the control of the link control circuit 10 as described later.

The local memory 60 reads and stores data of the host access control circuit 40, the link control circuit 10, and the overall control circuit 20 according to the control of the memory access control circuit 80, that is, the host access control. Although the circuit 40, the link control circuit 10, and the overall control circuit 20 each need to store and read data in the local memory 60, these circuits 40, 10, and 20 each store data. And a collision occurs when reading is performed, the memory access control circuit 80 receives a request signal from these circuits 40 and 10 20 and only one of them stores data in the local memory 60. It was configured to permit reading, and to permit data storage and reading in the local memory 60 to the other circuits 40, 10 20 only when a signal of completion of operation was applied from the permitted circuits 40, 10, 20.

A register circuit 50 is connected to the link control circuit 10. The register circuit 50 stores values necessary for the operation of the link control circuit 10, the overall control circuit 20, and the host 30. A number of registers are configured. That is, the register circuit 50 includes a register for a rate queue in which coefficient values that rate queues in the rate queue logic circuit 70 should count, are stored in the descriptor table area, the channel virtual channel table, in the local memory 60, And a base address register for storing the base addresses of the ready queue area and the completed queue area, and the like, and a pointer address register specifying an address to be stored and read in these tables. In addition, the register circuit 50 has an address queue of the descriptors Des 1-Des n in the local memory 60 which should start the transfer at the transfer rates of the respective rate queues in the rate queue logic circuit 70 as described below. It includes a register for storing the start descriptor address for each rate queue stored for each rate queue. The start address descriptor address of each rate queue will be described later in detail.

On the other hand, a plurality of rate queues are configured in the rate queue logic circuit 70 as described above, and these rate queues each count an internal clock signal, and are stored in registers for the rate queue in the register circuit 50. When the clock corresponding to the count value is counted, the transmission service request signal is configured to be applied to the overall control circuit 20. Here, the rate queue registers have different coefficient values stored for each rate queue, and thus the time points at which the transmission service request signal is applied for each rate queue are different.

The packet data conversion circuit 90 is connected to the host 30 through a packet data bus and a packet data control bus. The packet data conversion circuit 90 reads packet data of a packet buffer in the host 30 under the control of the overall control circuit 20. It is configured to apply to the cell buffer circuit 110. That is, the packet data conversion circuit 90 receives the address, the length, and the request signal of the packet buffer in which the packet data is stored from the general control circuit 10 and applies it to the host 30, and by the information, the host ( The packet data read by 30 is applied to the cell buffer circuit 110.

The cell buffer circuit 110 rearranges data from the packet data conversion circuit 90 in units of bytes according to the mode signal from the overall control circuit 20, and rearranges the rearranged data in units of 1 cell, that is, 48 bytes. Output That is, the CS / ATM circuit 120 to be described later processes the input data in units of one cell, but since packet data read from the host 30 is generally 32-bit units, these packet data are rearranged in byte units, and the CS / ATM circuit 120 The rearranged packet data is output in units of cells according to the read signal from the ATM circuit 120. Thus, it can be seen that the CS / ATM circuit performs the SAR function simultaneously.

The CS / ATM circuit 120 for inputting byte data from the cell buffer circuit 110 performs the functions of the CS layer and the ATM layer. Here, the cell data processed by the CS / ATM circuit 120 may be classified into two types. That is, it can be divided into general cell data and cell data which is the last part of the CPCS-PDU, and the CS / ATM circuit 120 processes the cell data differently according to the type of the cell data.

In the case of general cell data, after receiving the ATM header and the CRC intermediate value from the general control circuit 20, the cell data is received from the cell buffer circuit 110 to calculate the CRC value of the received cell data. After the ATM header is added to the received cell data, the ATM header is transmitted to the physical layer interface circuit 130, and the calculated CRC value is transmitted to the overall control circuit 20 to indicate that the processing for the received cell data is completed.

On the contrary, in the case of the cell data corresponding to the last part of the CPCS-PDU, the cell control circuit 110 after receiving the intermediate value of the ATM header and the CRC calculation from the control circuit 20 is instructed to be the last part of the CPCS-PDU. Receive cell data from Then, the length of the PAD data of the CPCS-PDU is inserted from the received cell data and attached to the cell data, and the CPCS-PDU is received from the overall control circuit 20. It receives the final length of and adds it to the cell data. In addition, the CS / ATM circuit 120 is configured to calculate and append a CRC to cell data, and to add an ATM header to the physical layer interface circuit 130 for transmission.

The cell data is converted into an ATM cell and applied to the physical layer interface circuit 130 by the CS / ATM circuit 120 described above. The physical layer interface circuit 130 transmits the ATM cell after processing the ATM cell corresponding to the physical layer transmission medium.

Next, the configuration of the link control circuit 10 for forming a descriptor link using the tables in the local memory 60 will be described.

6 shows an operation flowchart of the link control circuit 10.

As shown in the figure, the link control circuit 10 starts driving when the driving start signal LM_Start is applied from the overall control circuit 20 (step S1), and the pointer address register of the pointer address register configured in the register circuit 50 is started. The read pointer and the storage pointer are used to determine whether there are descriptors Des 1-Des n registered in the preparation queue (S2), and as a result of the determination of step S2, the registered descriptors Des 1-Des n do not exist. If all processes are terminated, if the registration descriptor (Des 1-Des n) exists, the address of the registration descriptor (Des 1-Des n) is read (S3).

The link control circuit 10 proceeds to step S4 to read the virtual channel table address stored in the virtual channel table area of the descriptors Des 1-Des n corresponding to the address read in the step S3, Information of the virtual channel tables VCT 1 to VCT n corresponding to the virtual channel table address is read (S4). In the virtual channel table VCT 1-VCT n, there is a number queue of rate queues in the rate queue logic circuit 70. The link control circuit 10 corresponds to a rate queue number stored in this rate queue number region. The address stored in the rate queue start descriptor address storage register of the rate queue to be read (this address means the address of the descriptors Des 1-Des n) is read (S5).

Here, there may be a case where an address is stored in the start descriptor address storage register for each rate queue and a case where the address is not stored. Therefore, the link control circuit 10 determines whether or not the address is stored in step S6 and stores it. If no, the process proceeds to step S7.

In step S7, the link control circuit 10 stores the address of the descriptor Des 1-Des n read in step S3 in a register for storing the start descriptor address per rate queue, and reads the read virtual channel table VCT. Also stored in the start descriptor address area of 1-VCT n) (S8).

However, as a result of the determination in step S6, when an address is stored in the register for storing the rate queue start descriptor address, the link control circuit 10 proceeds to step S9, where the descriptor Des 1-Des of the stored address is stored. Read n). Then, the link control circuit 10 stores the virtual channel whose address of the virtual channel table VCT 1-VCT n stored in the virtual channel table address area of the read descriptors Des 1-Des n is read in step S3. It is determined whether or not the address of the tables VCT 1 to VCT n is the same (S10).

As a result of the determination in step S10, if the addresses of the virtual channel tables VCT 1-VCT n are the same, the link control circuit 10 determines that the address in the NHD of the descriptors Des 1-Des n read in step S9 is equal to. It is determined whether "0" (here, 0 means a state in which no address is stored) (S11).

As a result of the determination in step S11, when the address in the NHD is not " 0 ", the link control circuit 10 reads the descriptors Des 1-Des n of the address written in the NHD (S12), and step S11. ), The above processes (S11, S12) are continued until the descriptors Des 1-Des n having " 0 " recorded in the NHD are detected.

As a result of the determination in step S11, if a descriptor (Des 1-Des n) having " 0 " written in the NHD is detected, the link control circuit 10 executes the step (N) of the descriptor (Des 1-Des n). The address of the descriptors Des 1-Des n read in S3) is stored (S13).

That is, the link control circuit 10 reads the descriptors Des 1-Des n registered in the preparation queue table in step S3, and the number of the rate queues assigned to the read descriptors Des 1-Des n. Is recognized from the virtual channel table (VCT 1-VCT n), and the first descriptor (Des 1 -Des n) to be transmitted at the transmission rate of the assigned rate queue is read out from the register for storing the start descriptor address per rate queue. When the virtual channels allocated to the read two descriptors Des 1-Des n are the same, the descriptor recorded in the NHD of the first descriptor Des 1-Des n to be transmitted at the transmission rate of the allocated rate queue ( Des 1-Des n) is read out, and a descriptor (Des 1-Des n) recorded in the NHD of this descriptor (Des 1-Des n) is successively performed (S11-S12). Here, when the descriptor address is not stored in the NHD of the descriptors Des 1-Des n read during the processes S11-S12, the descriptors Des 1-Des read from the preparation queue table in step S3. The address of n is recorded in the descriptor (NHD of Des 1-Des n) in which the address is not recorded by performing this process (S11-S12).

Therefore, the same rate queue is allocated in the NHD of the descriptors Des 1-Des n, and the addresses of the descriptors Des 1-Des n having the same virtual channel are stored.

On the other hand, when the determination result of step S10 indicates that the addresses of the virtual channel tables VCT 1-VCT n are different, the link control circuit 10 reads the NVD of the descriptors Des 1-Des n read out in step S9. It is determined whether my address is "0" (S14).

As a result of the determination in step S11, if the address of the descriptors Des 1-Des n other than " 0 " is recorded in the NVD, the link control circuit 10 returns to step S9 and the corresponding descriptor Des 1-. When Des n) is read out and the virtual channel table address of the read descriptors Des 1-Des n is different, "0" is recorded in the NVD of the descriptors Des 1-Des n by returning to step S14. The processes S9, S10, and S14 are continuously performed until the descriptor Des 1-Des n is detected.

On the other hand, if the descriptor Des 1-Des n in which "0" is recorded in the NVD is detected as a result of the determination in step S14, the link control circuit 10 writes to the NVD of the descriptor Des 1-Des n. The address of the descriptors Des 1-Des n read in step S3 is stored (S15).

That is, the link control circuit 10 reads the descriptors Des 1-Des n registered in the preparation queue table in step S3, and the number of the rate queues assigned to the read descriptors Des 1-Des n. Is recognized from the virtual channel table (VCT 1-VCT n), and the first descriptor (Des 1 -Des n) to be transmitted at the transmission rate of the assigned rate queue is read out from the register for storing the start descriptor address per rate queue. If the virtual channels allocated to the two read descriptors Des 1-Des n are different, the descriptors written in the NVD of the first descriptor Des 1-Des n to be transmitted at the transmission rate of the allocated rate queue ( The process of reading Des 1-Des n) and reading the descriptor recorded in the NVD of this descriptor (Des 1-Des n) is successively performed (S9, S10, S14). Here, when the descriptor address is not stored in the NVD of the descriptors Des 1-Des n read during the process S11-S12, the descriptors DES1-DESn read out from the preparation queue table in step S3. Is written into the NVD (the NVD of the descriptors Des 1-Des n in which the address is not recorded by performing steps S9, S10, and S14).

Therefore, the address of the descriptors Des 1-Des n having the same rate queue and different virtual channels is stored in the NVD of the descriptors Des 1-Des n.

FIG. 7 illustrates a state in which descriptors Des 1-Des n are mutually linked by an address of descriptors Des 1-Des n recorded in NHD and NVD of the descriptors Des 1-Des n through the above-described process. It is.

As shown, start addresses A-1 and C-1 of the descriptors Des 1-Des n are stored in the rate queue start descriptor address storage registers R1-Rn corresponding to each rate queue, respectively. It is. The address codes A-1 and B-1 in FIG. 7 are for convenience of explanation, and alphabetical characters such as A and B indicate the virtual channel table VCT 1-VCT n assigned to the descriptor. It is to.

As shown, an address of A-2 is recorded in the NHD in the descriptor Des A-1 corresponding to the start address in the register R1, and an address of A-3 is recorded in the NHD of the descriptor Des A-2. . Here, as described above, it can be seen that the descriptors Des A-1, A-2, and A-3 are assigned the same rate queue and the same channel A.

On the other hand, the address of the descriptor B-1 is stored in the NVD of the descriptor Des A-1, and is 0 in the NVD of the descriptor Des B-1, while the descriptor Des B-2 in the NHD. ) Is stored. Accordingly, it can be seen that the descriptors DesB-1 and B-2 have the same rate queues as those of the descriptors Des A1, A2 and A3, but the virtual channel VP is set to (B).

From the above description, the same rate queue and virtual channel C are set for the descriptor Des C-1 and the descriptor Des C-2 designated by the start address C-1 in the register R2. The descriptors Des D-1, D-2, and D-3 have the same rate queues as the descriptors Des C-1, but the virtual channels are different, and the descriptor Des E-1 is also the descriptor Des C-. It can be seen that the same rates as 1, C-2, D-1, D-2, and D-3) are set, but their virtual channels are different.

The link control circuit 10 storing the corresponding descriptors Des 1-n in the NHD and the NVD of the descriptors Des 1-Des n by performing steps S13 and S15 proceeds to step S8 described above. In the end descriptor number area of the virtual channel table VCT 1-VCT n corresponding to the descriptor Des 1-n read in step S3, the address of the descriptor Des 1-Des n of step S3 is recorded. And end all processes. On the other hand, the NVD and NHD in the descriptors Des 1-Des n of step S3 will be in a state of storing a "0" address, respectively. Here, the address in the end descriptor number area of the virtual channel table is stored after performing step S7 as described above.

After performing this process, the link control circuit 10 outputs a signal LM_done indicating that the process has been performed.

On the other hand, the rate queues in the rate queue logic circuit 70 output a transmission service request signal at different times as described above, and the overall control circuit 20 descriptors corresponding to the rate queues to which the transmission service request signal is applied. By transmitting the packet data of (Des1-n) ((this data is stored in the packet buffer of the host 30 as described above) into ATM cells, it is possible to transmit at a predetermined transmission rate.

8 shows an operational flowchart of the overall control circuit 20 performing this process.

As shown in the drawing, the overall control circuit 20 applies the driving signal described above to the link control circuit 10, that is, the LM_Start signal (S20), and then the termination signal LM_Done is applied from the link control circuit 10 ( S21) The drive starts.

That is, when the termination signal LM_Done is applied from the link control circuit 10, the overall control circuit 20 determines whether the transmission service request signal is applied from the rate queue in the rate queue logic circuit 70 (S22).

As a result of the determination in step S22, when the transmission service request signal is applied, the overall control circuit 20 starts the stored in the rate queue start descriptor address storage registers R1-Rn corresponding to the rate queue to which the transmission service request signal is applied. The address is read, and the virtual channel table (VCT 1-VCR n) information of the address recorded in the descriptor (Des 1-Des n) corresponding to this start address is read (S23).

In the virtual channel table VCT 1-VCT n, the count value area and the set value area exist as described above, and the overall control circuit 20 determines that the count value and the set value area of the count value area are different. In the same case, the transmission service is performed in response to the transmission service request signal. That is, as a result of the determination in step S24, the overall control circuit 20 increases the count value by one when the count value and the set value are different (S25), but goes to step S26 when the count value and the set value are the same. Proceeds to the transfer service as described below.

Therefore, even when the transmission time of the transmission service request signal of each rate queue is fixed, the transmission time of the descriptor Des 1-n is changed by changing the setting value in the virtual channel table VCT 1-VCT n. To change.

As a result of the determination in step S24, when the count value and the set value are the same, the overall control circuit 20 determines whether or not to receive the packet data from the host 30 (S26). That is, in order to receive packet data from the host 30 and to ATM cell, the process of forming a trailer such that the CPCS-PDU is a multiple of 48 bytes including the CPCS padding process (PAD), the trailer data by the process Is formed irrespective of packet data), and there is a case where it is not necessary to receive packet data from the host 30 by the data of this trailer.

If the overall control circuit 20 needs to receive the packet data from the host 30 as a result of the determination in step S26, the control circuit 20 proceeds to step S27 and needs to receive the packet data from the host 30. If no, the process proceeds to step S32.

The overall control circuit 20 proceeds to step S27 through the packet data conversion circuit 90 for the packet buffer start address and the packet buffer length stored in the descriptors Des 1-Des n read in step S23. By applying to the host 30, transmission of packet data corresponding thereto is required.

That is, the host 30 reads the packet data of the corresponding packet buffer by the packet buffer start address and the packet buffer length applied through the packet data conversion circuit 90 and applies the packet data to the packet data conversion circuit 90. The conversion circuit 90 applies the packet data to the cell buffer circuit 110 and then applies the write completion signal to the overall control circuit 20. The overall control circuit 20 determines whether the write completion signal is applied. It is judged in S28.

On the other hand, the overall control circuit 20 can know the length of the packet data applied from the host 30 to the cell buffer circuit 110 by the information transmitted in step S27, and the length (the number of bits) of this packet data. ) Forms one ATM cell to determine whether transmission is long or insufficient.

Therefore, the overall control circuit 20 determines whether one ATM cell can be formed by the length of packet data currently received in step S29, that is, it is 48 bytes, and if it is possible to form an ATM cell, If not, the process proceeds to step S30. That is, when the length of currently received packet data is insufficient in forming an ATM cell, the general control circuit 20 erases the descriptors Des 1-Des n designating the currently received packet data from the link structure of FIG. S30 and proceed to step S31. In step S31, the overall control circuit 20 re-determines whether the ATM cell can be formed as the length of the packet data received by the cell buffer circuit 110, and then proceeds to step S41 when the ATM cell cannot be formed. do.

In step S41, the overall control circuit 20 reads the descriptors Des 1-Des n stored in the NHD of the erased descriptors Des 1-Des n (S41), and reads the read descriptors Des 1-. The packet buffer start address, packet buffer length, and the like stored in n) are applied to the host 30 via the packet data conversion circuit 90 (S27). At this time, the packet buffer length to be transmitted to the host 30 is the length required to form the ATM cell (that is, the packet data received by the erased descriptors Des 1-n as a result of the determination in step 31). Is limited to the length that was insufficient to be formed). After transmitting the packet buffer start address and the limited packet buffer length in the descriptor Des 1-n as described above, the general control circuit 20 responds to the packet buffer length transmitted as described later in the descriptor Des 1-n. The packet buffer start address is changed and stored (S35).

On the other hand, when the overall control circuit 20 can form one ATM cell with the length of the packet data currently received as a result of the determination in step S29 and the packet data from the host 30 as a result of the determination in step S26. If there is no need to receive, steps S32 and S33 are performed sequentially.

That is, the overall control circuit 20 proceeds to step S32 to determine the ATM header, the median value of the CRC, the transmission length, and the like stored in the virtual channel tables VCT 1-VCT n and the descriptors Des 1-Des n. Information about the CS / ATM circuit 120 and then a driving signal, that is, a CS / ATM_Srart signal.

Based on the above information, the CS / ATM circuit 120 performs the function of the CS layer and the ATM layer, that is, the addition of the header and the calculation and addition of the trailer of the CPCS-PDU, and thus the end signal, that is, the CS / ATM_Done signal. Is applied to the overall control circuit 20.

Here, the packet data processed by the CS / ATM circuit 120 may be classified into three types as follows.

1. The data for transmission no longer exists in the packet buffer indicated by the descriptor (Des 1-Des n) indicating the packet data currently being processed, and the currently transmitted data is not the last part of the CPCS-PDU.

2. The data for transmission no longer exists in the packet buffer indicated by the descriptor (Des 1-Des n) indicating the packet data currently being processed, and the currently transmitted data is the last part of the CPCS-PDU.

3. Finally, there is more data for transmission in the packet buffer indicated by the descriptor (Des 1-Des n) indicating the packet data currently being processed.

The operation performed by the overall control circuit 20 according to these conditions should be different, and the overall control circuit 20 performs the following process.

That is, the overall control circuit 20 determines whether the aforementioned CS / ATM_Done signal is applied in step S33, and proceeds to step S34 when the CS / ATM_Done signal is applied.

In step S34, the overall control circuit 20 determines whether there is further data in the packet buffer indicated by the descriptors Des 1-Des n indicating the packet data currently being processed. If none exists, the flow advances to step S36.

Since the overall control circuit 20 proceeds to step S35 because this case is the result of the performance of step S41, the overall control circuit 20 proceeds within the descriptor Des 1-Des n corresponding to the packet buffer length transmitted in step S27. The packet buffer start address is changed and stored, and the flow proceeds to step S38 (S35).

However, when there is no data in the packet buffer indicated by the descriptor (Des 1-n) indicating the packet data currently being processed, the general control circuit 20 determines whether the packet data currently being processed is the last part of the CPCS-PDU. (S36), if it is not the last part, proceeds to step S30 described above, thereby erasing the descriptor (Des 1-Des n) designating the packet data being processed (S30) and proceeds to step S31 described above. do.

On the other hand, since the CRC calculation should be terminated when the packet data currently being processed is the last part of the CPCS-PDU as a result of the determination in step S36, the overall control circuit 20 proceeds to step 37 to reset the CRC value. The process proceeds to step S30 described above.

After performing the above-described steps S25, S35, and S36, the overall control circuit 20 proceeds to step S38. Here, the state after performing the steps S25, S35, and S36 is the descriptor Des 1-Des. Since the transmission of the packet data of the host 30 designated by n) is completed, the overall control circuit 20 changes the contents, that is, the count value, in the virtual channel table VCT 1-VCT n for the transmitted packet data. After the CRC value is rewritten, the process proceeds to step S39.

In step S39, the overall control circuit 20 reads the NVD of the descriptors Des 1-Des n which have been transferred, and if the address of the descriptors Des 1-Des n is stored in this NVD, In step S23), the above-described process is repeated, but if no address is stored in the NVD, all processes are terminated.

That is, when the LM_done signal is applied from the link control circuit 10 and the transmission request signal is applied from a predetermined rate queue in the rate queue logic circuit 70, the general control circuit 20 of the present invention provides a link shown in FIG. According to the structure, the packet data of the descriptors Des 1-Des n are sequentially transmitted.

For example, in the case where the rate queue corresponding to the register R2 in the link structure of FIG. 7 outputs a transfer request signal, the overall control circuit 20 may store packets of the descriptor Des C-1 stored in the register R2. Data is read from the host 30 and transmitted, and packet data of the descriptor Des D-1 stored in the NVD of the descriptor Des C-1 is sequentially read from the host 30 and transmitted, and the descriptor Des The packet data of the descriptor Des E-1 stored in the NVD of D-1) is read from the host 30 and transmitted. Here, since the address of the descriptors Des 1-Des n is "0" in the NVD of the descriptor Des E-1, no further packet data is transmitted, and the descriptor Des C-1 that has transmitted the packet data. , D-1, E-1) are erased in the link structure of FIG. The packet data of the descriptors Des C-2 and D-2 are supplied to the overall control circuit 20 when the rate queue corresponding to the register R2 applies the transmission request signal to the overall control circuit 20 again. The packet data of the descriptors Des C-2 and D-2 will be read from the host 30 and transmitted.

Through the above-described process, the data output from the CS / ATM circuit 120 is in an ATM cellized state, and the physical layer interface circuit 130 processes these ATM cells in correspondence with the physical layer transmission medium and then transmits the data.

That is, the link control circuit 10 in the present invention forms a link corresponding to the transmission channel and the rate queues for the packet buffer of the host 30, and the overall control circuit 20 corresponds to the link of the packet buffer. The data is read and processed by AAL type 5 and ATM layers.

As described above, the present invention has an effect of easily realizing a hardware configuration for transmitting ATM cells by performing AAL type 5 processing and ATM layer processing of host data.

Claims (14)

An asynchronous transmission mode (ATM) cell transmission device of asynchronous transmission mode adaptation layer type 5, A host for storing packet data for transmission in internal packet buffers and for transmitting data in a read requested packet buffer; A local memory in which information about packet buffers of the host is stored; A plurality of rate queues are stored, the rate queues comprising: a rate queue logic circuit for counting an internal clock to a differently designated count value and outputting a transmission request signal at different times; A link control circuit for mutually linking packet buffers for transmission at a transmission rate corresponding to the rate queue using information stored in the local memory for each rate queue and transmission channel; When the transmission request signal is applied, read requests are sequentially made to packet buffers having different transmission channels among the packet buffers linked in correspondence with the rate queue that outputs the transmission request signal, and the read buffer packets A total control circuit for erasing from the link; A cell buffer circuit for assembling and outputting packet data from the host in units of cells; A CS / ATM circuit which inputs data from the cell buffer circuit and performs processing on the common part convergence sub-layer and the ATM layer on the input data; And a physical layer interface circuit configured to physically process and transmit the output of the CS / ATM circuit. The method of claim 1, ATM cell transmission device of asynchronous transfer mode adaptation layer type 5, connected to the host, further comprising a host access control circuit configured to store and read information about a packet buffer in the local memory according to control from the host. . The method of claim 2, A packet configured between the host and the cell buffer circuit, applying a read request signal for a packet buffer to the host under control of the global control circuit, and applying packet data from the host to the cell buffer circuit. An ATM cell transmission device of asynchronous transmission mode adaptation layer type 5, further comprising a data conversion circuit. The method of claim 3, wherein And a memory access control circuit for mediating access to said local memory of said host, said aggregate control circuit and said link control circuit. The method of claim 4, wherein the local memory, An area of descriptors which respectively store information about the packet buffer; An area of virtual channel tables in which information about a virtual channel to which data in the packet buffers should be transmitted is stored; An area of ready queues in which addresses of descriptors which are requested to be transmitted among the descriptors are stored; And an ATM cell transmission apparatus of an asynchronous transmission mode adaptation layer type 5 having an area of completion queues in which addresses for the completed transmissions of the descriptors are stored. 6. The method of claim 5, wherein the descriptor is A start address storage area of a packet buffer in which a packet to be transmitted by the host is stored; A packet buffer length storage area indicating a length of the packet buffer to be transmitted; A cumulative length storage area indicating a data length of the common-convergence sublayer-protocol data unit (PDU); A descriptor mode storage area including bits indicating a type of a packet, a PTI value included in a cell header, and whether the packet is the last packet of a CPCS-PDU, and storing bits used for cell transmission; A Next Vertical Descriptor Address (NVD) in which an address of the same rate queue is assigned but stores addresses of descriptors having different virtual channels; An adjacent horizontal descriptor area (NHD) in which an identical rate queue is allocated and an address of a descriptor having the same virtual channel is stored; An area for storing byte length information to be read; And asynchronous transmission mode adaptation layer type 5 ATM cell transmission device having an address storage area of said virtual channel tables. The method of claim 6, wherein the virtual channel table, An ATM cell header information area required for ATM cellization of the transmitted packets; A counting value area for counting and storing an output number of transmission service request signals of a predetermined rate queue in said rate queue logic circuit; A setting value area storing a setting value for counting the service request signal; A CRC result value area for storing a result value by performing a cyclic redundancy check (CRC) upon ATM packetization of the packet data; A header addition notification area indicating whether the packet data to be transmitted is data to be transmitted by adding a header or whether to transmit the packet data as received from the host without the header; A rate queue number area indicating which rate queue of said rate regulation logic circuit the corresponding channel transmission rate of said packet data belongs to; A start descriptor number area for storing an address of a descriptor among the descriptors, the buffer specifying a buffer to start transmission in accordance with a transmission request signal of the rate queue; And an end descriptor number field for storing an address of a descriptor which specifies a buffer of which the transmission should be terminated in accordance with the transmission request signal of the rate queue, among the descriptors. The method of claim 7, wherein A rate queue register for storing coefficient values that rate queues in the rate queue logic circuit should count; A base address register storing base addresses of a descriptor table area, a virtual channel table area, a ready queue area, and a completion queue area in the local memory; A pointer address register specifying an address to be stored and read / read in said descriptor table area, virtual channel table area, ready queue area and completion queue area; An asynchronous transfer mode adaptation layer type further comprising a register circuit having a register for storing rate-based start descriptor address for storing, for each rate queue, an address of the descriptor which should start transmission at the rate of transmission of each rate queue in the rate queue logic circuit. 5, ATM cell transmitter. Descriptors having an address area, a next horizontal descriptor area (NHD), and a next vertical descriptor area (NVD) of a packet buffer in a host, in which a packet to be transmitted in a local memory is stored, Virtual channel tables storing the virtual channel and the corresponding rate queue to which packets in the packet buffer are to be stored, and preparation queues storing the addresses of the descriptors are stored, and rate queues having different transmission time points are respectively stored. A method of linking descriptors in the local memory according to a transmission time point in an ATM cell transmission apparatus of an asynchronous transmission mode adaptation layer type 5 assigned an address of a different starting descriptor. A first descriptor reading step of reading a descriptor in the preparation queue; A second descriptor reading step of reading a virtual channel table corresponding to a virtual channel table address stored in the read descriptor and reading an address of a start descriptor assigned to the rate queue stored in the virtual channel table; Determining whether the virtual channel addresses of the descriptors read in the first and second descriptor reads are the same; If the virtual channel addresses of the descriptors read in the first and second descriptor reading steps are the same, the descriptors stored in the NHD of the descriptor are sequentially read from the descriptor allocated to the rate queue, and the address of the descriptor is stored in the NHD. A first descriptor address storing step of storing an address of a descriptor read in the first descriptor reading step in a descriptor not written; If the virtual channel addresses of the descriptors read in the first and second descriptor read step are different, the descriptors stored in the NVD of the descriptor are sequentially read from the descriptor allocated to the rate queue, and the descriptor address is stored in the NVD. And a second descriptor address storing step of storing an address of a descriptor read in the first descriptor reading step in an undescripted descriptor. The method of claim 9, If the address of the start descriptor allocated to the rate queue does not exist as a result of performing the second descriptor read step, the address of the descriptor read in the first descriptor read step is allocated to the rate queue as a start descriptor address. The ATM cell transmission method of the asynchronous transmission mode adaptation layer type 5 further comprising a start descriptor address assignment step. Next Horizontal Descriptor Address (NHD) and Same Rate Queue, where the address of the packet buffer in the host, the same rate queue, and the address of the descriptor to which the same channel is stored are stored in the local memory. Descriptors having a Next Vertical Descriptor Address (NVD) where addresses of descriptors to which different channels are allocated are stored, and virtual channel tables storing a virtual channel to which the packet buffer should be transmitted and a corresponding rate queue. And rate queues having different transmission time points are generated by using the descriptors linked through the NHD and the NVD in the ATM cell transmission apparatus of the asynchronous transmission mode adaptation layer type 5, to which addresses of different start descriptors are assigned. ATM data in buffer As a method of reading to sel A transmission request determination step of determining whether there is a transmission request from one of the rate queues; A data transfer request step of requesting the host for data transfer of a packet buffer corresponding to an address stored in a start descriptor corresponding to the rate queue, if there is a transfer request from the rate queue; ATM cellization by adding a header and a trailer to the packet data transmitted from the host to ATM cellization, and transmitting the same to a physical transmission medium; A descriptor erasing step of erasing from the local memory a link of the descriptor specifying the address of the packet buffer in which the data transfer is completed; An NVD determining step of determining whether an address exists in the NVD of the descriptor for which the transfer is completed; If there is an address in the NVD, an asynchronous transfer mode is provided, which reads a descriptor of the address, and sends a packet buffer corresponding to the address stored in the descriptor to the host and then returns to the ATM cellization step. ATM cell transmission method of adaptation layer type 5. The method of claim 11, A coefficient value storage area and a setting value storage area exist in the table of the virtual channel, and after performing the transmission request determining step, it is determined whether the transmission request has been requested the number of times corresponding to the setting value. If it is not required to correspond to the number of times to increase the coefficient value by 1 and proceeds to the NVD determination step, and if required to the number corresponding to the set value, further comprising a transmission time determination step of proceeding to the data transmission request step Asynchronous transmission mode adaptation layer type 5 ATM cell transmission method. The method of claim 12, After performing the transmission time determining step, it is determined whether data transmission from the packet buffer of the address specified by the descriptor is necessary, and if host data is required, proceeds to the data transmission request step, and if no host data is needed, the ATM cellizing step. The ATM cell transmission method of the asynchronous transmission mode adaptation layer type 5, further comprising the data need determination step of proceeding. The method of claim 13, An ATM cell possibility determination step of determining whether one ATM cell can be formed as data of a packet buffer currently received after performing the data transmission request step; As a result of performing the ATM cell determination step, if formation of one ATM cell is not possible, the required amount of data transfer is resumed from the packet buffer specified in the descriptor of the address written in the NHD of the descriptor specifying the packet buffer in which the current data was received. Requesting data retransmission request; Determining whether there is more data to be transmitted to the packet buffer indicated by the descriptor indicating the packet data currently being processed after the ATM slicing step, and if there is no more data, proceeding to the descriptor erasing step Wow; As a result of performing the data existence determination step, if there is further data, an address change setting step of changing and setting the address of the packet buffer indicated by the descriptor indicating the packet data currently being processed to the address of the packet buffer in which the data exists is further performed. The ATM cell transmission method of the asynchronous transmission mode adaptation layer type 5 provided.