KR0153924B1 - Packet data dividing/reassembling apparatus and method for aal-5 service - Google Patents

Abstract

The present invention relates to an apparatus and method for packet data separation / recombination for an ATM adaptation layer type 5 service. The present invention relates to a method for transmitting and storing a table relating to a start address and a current address of a packet memory 1, a length of packet data, and the like. Reception control table means 12; CPU interface means 13 for matching with the CPU 2; Memory interface means (11) for inputting and outputting control signals through the CPU interface means (13), and for transmitting and receiving packet data to and from the packet memory (1) by a control signal for transmitting and receiving packet data; A transmission data reception signal from the memory interface means 11 to receive packet data, transmission with a cell header added thereto, and a transmission read completion signal to the memory interface means 11 when the transmission is completed. Packet separation means 20; And receiving packet recombination means 30 which receives packet data from the outside, separates the cell headers, and outputs an address to output the packet data to the memory interface means 11. It can be easily implemented without external control memory, and there is no limit on the data length by user defined and used packet memory size up to 65536 bytes, and variable bit using AAL Type 5 because of simple implementation. In addition to improving the data processing capacity when accommodating various services, the number of gates of the chip can be reduced and the implementation time can be shortened.

Description

Packet data separation / recombination apparatus and method for ATM adaptation layer type 5 service

1 is a schematic configuration diagram of a packet data separation / recombination apparatus according to an embodiment of the present invention.

2 is an overall flowchart for packet data separation / recombination according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: control unit 20: transmission packet separation unit

30: Receive packet recombination unit

The present invention relates to an apparatus and method for packet data separation / recombination for ATM adaptation layer type 5 service.

The ATM Adaptation Layer (AAL) is divided into a Convergency Sublayer (CS) and a Segmentation And Reassembly (SAR) layer. The convergence layer is divided into a common part convergence sublayer (CPCS) and a service specific convergence sublayer (SSCS) to perform transmission error detection and higher layer service processing. The separation and recombination layer separates service data (CPCS-PDU) input from the upper layer (CPCS) into a 48-byte ATM cell payload and converts other types of cell payload received from the ATM layer. Recombines service data.

Conventionally, separate control memory for memory management and packet memory for storing data are separately implemented for the above separation and recombination, and the algorithm itself has a complicated problem.

The present invention devised to solve the above problems of the prior art can be simply implemented without an external control memory when the number of possible connections is fixed at the same time, the maximum size of the packet memory as desired 65536 bytes (ITU-T The maximum packet size defined in I.363 can be defined by the user, so that the data length is unlimited and the implementation method is simple, improving the data processing capacity when accommodating various services of variable bits using AAL Type 5 An object of the present invention is to provide a packet data separation / recombination device and method capable of reducing the number of gates of a chip and shortening an implementation time.

The present invention for achieving the above object is a transmission / reception control table means for storing and outputting a table relating to the start address and the current address of the packet memory required for each connection, the length of the packet data; CPU interface means for receiving a control signal and data from a CPU, interpreting and outputting the control signal, and receiving and transmitting a control signal to be transmitted to the CPU; A memory interface means for inputting / outputting a control signal through the CPU interface means and accessing data of the transmission / reception control table means to transmit and receive packet memory and packet data by a control signal for transmitting and receiving packet data; Receives a transmission data signal from the memory interface means, receives a memory bus for reading data, outputs an address to the memory interface means, receives packet data, transmits with a cell header, and transmits when transmission is complete. Transmission packet separation means for outputting a read completion signal to the memory interface means; And receiving packet data from the outside and outputting a reception data existence signal to the memory interface means, receiving a write write authorization signal indicating a memory bus usage permission from the memory interface means, separating a cell header, and outputting an address. And receiving packet recombination means for outputting packet data to the memory interface means.

In addition, in the packet data separation / recombination method applied to a packet data separation / recombination device for an ATM adaptive layer type 5 service, a memory bus request signal and a memory bus busy signal are initialized, and if there is received data, received data is received. After receiving the memory bus to write to the packet memory, it asserts the memory busy signal by asserting the memory busy signal, reads the current address for the connection from the transmit / receive control table, and writes 47 bytes of data into the packet memory. After updating the incremented address to the current address of the table, if the reception procedure is completed, the received data is the last data of the packet data. If there is no error in the received packet data, the received data is valid. First step of writing; And if there is data to be transmitted, the memory bus is applied through the transmit read request signal and the transmit read signal, asserting that the memory in use signal is in use, and indicating the start of the connection in the transmit / receive control table. After reading the length of the packet and using it to read the data from the packet memory and separating it into 48-byte cell payload, read the connection information about the packet from the transmit / receive control table and make a 5-byte cell header. And a second step of generating a 53-byte ATM cell header by adding a cell header to the separated cell payload, and notifying that the transmission procedure is completed when the read is completed.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a schematic configuration diagram of a packet data separation / recombination apparatus according to an embodiment of the present invention, in which 1 is a packet memory, 2 is a CPU, 3 is a packet data separation / recombination apparatus according to the present invention, and 10 is The control unit 20 denotes a transmission packet separation unit and 30 denotes a reception packet recombination unit.

The separation / recombination apparatus 3 of the present invention outputs and stores packet data to and from the packet memory 1 under the control of the CPU 2. The present invention is composed of a control unit 10 for informing the management and status of the packet memory 1, a transmission packet separation unit 20 and a reception packet recombination unit 20 in association with transmission and reception, respectively. The control unit 10 includes a memory interface unit 11 for performing an interface between the transmission packet separation unit 20, the reception packet recombination unit 30, and the packet memory 1, the transmission / reception control table 12, and the CPU 2. ) Is a CPU interface unit 13 which transmits a control signal through matching with) or receives a control signal and interprets and outputs the control signal to the memory interface unit 11. The memory interface unit 11 has a function for selecting addresses and data input and output from the transmission packet separation unit 20 and the reception packet recombination unit 30 or accessing the packet memory 1. The transmission / reception control table 12 manages a table relating to a start address and a current address of the packet memory 1 required for each connection, length of packet data, and the like, for separation and recombination. The CPU interface unit 13 interprets or creates signals necessary for interfacing with the CPU.

If there is service data to be transmitted from the upper layer, data is written to the packet memory 1 for each service data unit, and the CPU 2 recognizes that there is data to be transmitted to the packet memory 1, and then a control signal for reading the data. The in address, the address strobe signal, the chip select signal, and the read select signal are notified to the controller 10 through the CPU interface unit 13. The CPU interface unit 13 of the control unit 10 notifies the memory interface unit 11, and the memory interface unit 11 reads the transmission / reception control table 12 and transmits a transmission data present signal to the transmission packet separation unit. Pass in 20. When this signal is asserted 'low', the transmission packet separation unit 20 knows that there is data to transmit and prepares to read the service data in the packet memory 1. First, the memory interface unit 11 of the control unit 10 requests the use of the memory bus through the CPU interface unit 13 through the transmission read request signal. That is, the CPU 2 is informed via the memory bus request signal. When the memory bus application signal allowing the CPU 2 to use the memory bus is asserted, the control unit 10 asserts and transmits a transmission read authorization signal to the transmission packet separation unit 20. The transmission packet separation unit 20 asserts a signal during transmission read and transmits the signal to the control unit 10, and the control unit 10 asserts a memory bus busy signal to the CPU 2 again, and the packet memory 1 Indicates that reading data is being read from. The transmission packet separation section 20 outputs a chip selection signal, an address, and a read selection signal to the packet memory 1 through the initial address of the transmission data and the length of the transmission data of the transmission / reception control table 12 set by the CPU. Service data stored in the packet memory 1 is read. After reading the service data, the transmission packet separation unit 20 negates the transmission read request signal and the transmission read signal to 'high' and asserts the transmission read completion signal to read the data. Notify the control unit 10. The controller 10 recognizes these signals, negates the memory bus request signal and the memory bus busy signal to high, and asserts a bit indicating completion of transmission of the transmission / reception control table 12 to transmit packets. Finally, it tells the CPU 2 that it has finished reading.

Conversely, when there is data to be transmitted from the received packet recombination unit 30 to the upper layer, the reception recombination unit 30 asserts that there is data to be transmitted to the packet memory 1 by asserting the reception data present signal and receiving a write write request signal. Through the start of the memory bus request procedure as in the transmission packet separation section 20. When the reception write authorization signal, which is the memory bus usage authorization signal, is asserted, the reception packet recombination unit 30 asserts a signal during reception writing and transmits it to the controller 10, and the controller 10 again uses the memory bus busy signal. Asserts that it is writing the received data to the packet memory 1.

The reception packet recombination section 30 selects a chip select signal, an address, and a write selection to the packet memory 1 through the initial address of the reception data and the length of the reception data of the transmission / reception control table 12 set by the CPU 2. A signal is output and the received data is written to the packet memory 1. After the received data has been exhausted, the received packet recombination unit 30 negates the received write request signal and the received write signal to 'high', asserts the received write complete signal, and then the controller 10 runs out of data. Notify

The controller 10 recognizes these signals and negates the memory bus request signal and the memory bus busy signal to 'high'. In addition, the control unit 10 confirms whether the received data written now is the last data of the original packet data, and if it is the last data, asserts a bit indicating completion of reception of the transmission / reception control table 12 and exhausts the received packet. Is finally informed to the CPU 2. The received packet recombination unit 30 checks the error of the packet data and informs the CPU 2 of the error state through the transmission / reception control table 12.

2 is a flowchart illustrating the separation and recombination of transmitted and received packet data according to an embodiment of the present invention.

First, in the idle state, the memory bus request signal and the memory bus busy signal are negated and initialized (100). The received packet recombination unit 30 checks whether there is data to be recombined in the packet memory 1 (110), and if there is data, maps the receive write request signal and the receive write signal to the memory bus request signal and the memory bus busy signal, respectively. After that (120), the use of the memory is required to write the received data to the packet memory (1) (130). When the memory bus grant signal indicating permission of the memory usage is received from the CPU 2 (140), the memory busy signal is asserted to inform the reception packet recombination unit 30 that the memory is being used (150). Then, 47 bytes of received data are written to the packet memory 1 (160). At this time, the current address for the corresponding connection is read from the transmit / receive control table 12, and 47 bytes of data are read into the packet memory (1). ) And update the 47 increased address to the current address of the table. The memory busy and memory request signals are notified that one cycle of the reception procedure (defined here as writing data into the memory in units of 47 bytes) is completed (170). If the received data is the last data of the packet data, that is, whether the packet data has been recombined, it is checked (180). If the received data is finished, the received data is checked for errors (190). Check if data is present (110).

If there is no error in the received packet data, the transmission / reception control table 12 notifies that the received data is valid (200). If an error occurs, an error occurs in the received data, and the received packet data is discarded or a packet is sent with a tag (210).

If there is no received data to be recombined, it is checked whether there is data to be transmitted from the packet memory 1 to the transmission packet separation section 20 (220). If there is data to be transmitted, the transmit read request signal and the transmit read signal are mapped to the memory bus request signal and the memory bus busy signal, respectively (230). After requesting memory use so that transmission data can be read from the packet memory 1 (240), and receiving a memory bus authorization signal indicating permission of memory use from the CPU 2 (250), the memory busy signal Asserts that the transmission packet separation unit 20 is using the memory (260). After reading the start address and the packet length of the corresponding connection from the transmission / reception control table 12, the transmission packet separation unit 20 reads data from the packet memory 1 based on the 48-byte cell. Separate in payload form. At this time, the connection information about the packet is also read from the transmission / reception control table 12 to form a 5-byte cell header, and the 53-byte ATM cell header is generated by adding the cell header to the separated cell payload ( 270). When the read operation is completed, a notification indicating that the transmission stop is completed is performed by neglecting the memory in use and the memory request signal (280).

The present invention configured and operated as described above can be simply implemented without an external control memory when the number of possible connections is fixed at the same time. The maximum size of the packet memory is 65536 bytes (Maximum defined in ITU-T I.363). By defining and using Packet Size), there is no limitation on the length of data, and the implementation method is simple, which improves the data processing capacity when accommodating various services of variable bits using AAL Type 5 and reduces the number of gates of the chip. This can reduce the implementation time.

Claims (4)

Transmission / reception control table means 12 for storing and outputting a table relating to the start address and the current address of the packet memory 1 required for each connection, the length of the packet data, and the like; CPU interface means (13) for receiving control signals and data from the CPU (2), interpreting them, outputting them, and receiving and transmitting the control signals to be transmitted to the CPU (2); Input / output of a control signal through the CPU interface means 13, and accessing data of the transmission / reception control table means 12 to transmit and receive packet data with the packet memory 1 by a control signal for transmitting and receiving packet data. Memory interface means 11; Receives a transmission data signal from the memory interface means 11, receives a memory bus for reading data, outputs an address to the memory interface means 11 to receive packet data, and transmits by adding a cell header. Transmission packet separation means (20) for outputting a transmission read completion signal to the memory interface means (11) when transmission is completed; And receiving the packet data from the outside and outputting a signal that there is received data to the memory interface means 11, receiving a write write authorization signal from the memory interface means 11 indicating the permission to use the memory bus, and receiving a cell header. A packet data separation / recombination device for an ATM adaptation layer type 5 service, characterized in that it comprises a receiving packet recombination means 30 which outputs an address after separation and outputs packet data to the memory interface means 11. . A packet data separation / recombination method applied to a packet data separation / recombination device for an ATM adaptation layer type 5 service, the method comprising: initializing a memory bus request signal and a memory bus busy signal, and receiving data into a packet memory ( After receiving the memory bus for writing to 1), it asserts the memory busy signal by asserting the memory busy signal, and reads the current address of the corresponding connection from the transmission / reception control table 12 to read 47 bytes of data. Is written into the packet memory 1, the 47 is increased to the current address of the table, and when the reception procedure is completed, the received data is the last data of the packet data, and if there is no error in the received packet data, the received data is valid. A first step (100 to 210) for notifying the transmission / reception control table 12 by writing to it; And if there is data to be transmitted, the memory bus is applied through the transmit read request signal and the transmit read signal, asserting that the memory busy signal is in use, and informing the corresponding connection in the transmit / receive control table 12. Reads the start address and the length of the packet, reads data from the packet memory (1), separates them into 48-byte cell payloads, and reads connection information about the packet from the transmit / receive control table (12). After the 5-byte cell header is created, a 53-byte ATM cell header is generated by adding the cell header to the separated cell payload, and when reading is completed, a second step 220 to 280 indicating that the transmission procedure is completed is included. Packet data separation / recombination method for an ATM adaptation layer type 5 service. 3. The third step according to claim 2, wherein the memory bus request signal and the memory bus busy signal are negated and initialized in the holding state, and the received packet recombination means 30 checks whether there is data to be recombined to the packet memory 12. (100, 110); If there is data in the third step (110, 110), the memory is used to write the received data to the packet memory 1 by mapping the received write request signal and the received write signal to the memory bus request signal and the memory bus busy signal, respectively. A fourth step (120 to 140) of waiting for a memory usage authorization signal to be received after requesting the request; When the memory bus applying signal is received from the CPU 2 in the fourth step 120 to 140 (140), the memory busy signal is asserted to indicate that the memory is being used, and the corresponding signal is transmitted in the transmission / reception control table 12. Reads the current address for the connection, writes 47 bytes of data into the packet memory (1), updates the 47 incremented address to the current address in the table, and indicates that the memory busy and memory request signals A fifth step (150 to 180) of negating to inform and determining whether the received data is the last data of the packet data; And in the fifth step (150 to 180), if the packet data is the last, check whether the packet is error. If there is no error in the received packet data, it notifies the transmission / reception control table 12 by writing that the received data is valid. In case of occurrence, the ATM adaptation layer type 5 service includes a sixth step (190 to 210) informing the occurrence of an error of the received data, and discarding the received packet data or tagging and sending the packet as an error packet. Packet data separation / recombination method. 3. The second step (220 to 280), if there is data to be transmitted from the packet memory (1) to the transmission packet separation means 20, the memory bus request for the transmission read request signal and the transmission read signal, respectively A seventh step (220 to 250) of requesting a memory bus to receive a memory bus authorization signal after requesting the memory to be able to read the transmission package data by mapping the signal to a signal in use of the memory bus; And receiving a memory bus grant signal indicating permission of memory use from the CPU 2 in the seventh step 220 to 250, asserting that the memory busy signal is being used, and transmitting / receiving control table. After reading the start address and the packet length for the corresponding connection in (12). By using this, data is read from the packet memory 1 and separated into a 48-byte cell payload. At this time, the connection information about the packet is also read from the transmit / receive control table 12 and the 5-byte cell header is read. After made. Eighth step (260 to 260 through adding a cell header to the separated cell payload, generating and outputting a 53-byte ATM cell header, and notifying a memory busy signal and a memory request signal that the transmission procedure is completed when reading is completed). Packet data separation / recombination method for an ATM adaptation layer type 5 service, comprising: