KR100381377B1 - ATM Interfacing Apparatus Having Received Cell Header Conversion Apparatus - Google Patents

Abstract

The present invention relates to an ATM matching device having a receiving cell header conversion device capable of supporting a VPI / VCI full-range required by an ATM network.

Conventionally, the range of VPI / VCI designation that APC can accept for each MPHY is allowed from 0 to a certain VPI / VCI value. Therefore, in order to access and use multiple access gateways in one ATM network, each gateway has a different area. As service providers who want to assign VPI / VCI addresses cannot use a high range of VPI / VCI addresses, they cannot use the network efficiently because service providers must configure networks with only a limited range. There is a problem of becoming complicated.

The present invention converts the full-range VPI / VCI value included in the header of a cell received from the network side into a VPI / VCI value of the specified range that APC can accept and transmits the result to the APC network. By supporting the full range of VPI / VCI required in the system, VPI / VCI can be efficiently assigned by region or gateway, and even if a high value is assigned, As a result, network configuration and network management can be efficiently operated.

Description

ATM Interfacing Apparatus Having Received Cell Header Conversion Apparatus

The present invention relates to an ATM matching device having a receiving cell header conversion device, and more particularly, to an ATM matching device having a receiving cell header conversion device capable of supporting a full range of VPI / VCI required by an ATM network. Relates to a device.

In general, an access gateway that is matched to an Asynchronous Transfer Mode (ATM) network includes an ATM matching device for matching with an ATM network.

1 illustrates a road, an ATM matching device 10, an ATM matching layer 5 processing unit 70, or an AAL2 processing unit 80 or 90 showing an example of a configuration of an ATM matching board of an access gateway matched to an ATM network. It is provided with.

As described above, the ATM matching device 10 uses the AAL5 processing unit 70 or the AAL2 processing unit 80 or 90 to transfer an ATM cell received from a power station through an ATM network through an optical transceiver (not shown) according to the connection information. The cell received from the AAL5 processor 70 or the AAL2 processor 80 or 90 is transmitted to the network side according to the connection information.

FIG. 2 is a road showing an example of the configuration of the ATM matching device 10 of FIG. 1, a Synchronous Transfer Mode (STM) -1 framer 15, a local memory 20, and a look-up table. Table) memory 25, cell buffer memory 30, ATM port controller (APC), first transmit / receive first in first out (FIFO) 40a, first high speed serial bus 45a, A second transmit / receive FIFO 40b, a second high-speed serial bus 45b, a third transmit / receive FIFO 40c, a third high-speed serial bus 45c, a transmit / receive FIFO control unit 50, a high-speed serial bus The control unit 55 and the CPU 60 are provided.

In such a configuration, the STM-1 framer 15 accommodates two STM-1 links (STM-1 link 1 and STM-1 link 2), and receives the input frame when the cell is input in the form of a frame through the link. It extracts ATM cells and directly matches them with APC 35 and UTOPIA (Universal Test and Operation PHY Interface for ATM), converts ATM cells received from APC 35 into frames, and transmits them to the network through the link.

The local memory 20 stores application programs.

The look-up table memory 25 stores connection information for port control.

The cell buffer memory 30 is a buffer for temporarily storing cells when the APC 35 obtains port control connection information from the look-up table memory 25. After all cells are stored in the cell buffer memory 30, the cell buffer memory 30 is stored in the cell buffer memory 30. It is switched according to the connection information.

The transmission / reception FIFO control unit 50 controls the first transmission / reception FIFO 40a, the second transmission / reception FIFO 40b, and the third transmission / reception FIFO 40c.

The high speed serial bus controller 55 controls the first high speed serial bus 45a, the second high speed serial bus 45b, and the third high speed serial bus 45c.

The APC 35 stores the port control connection information received from the CPU 60 in the look-up table memory 25, and stores the cell received from the network side through the STM-1 framer 15 in the look-up table memory ( According to the connection information stored in 25), it transmits to the corresponding AAL processing unit through the corresponding sending / receiving FIFO and the high speed serial bus, and if the cell sent from the specific AAL processing part is stored in the sending / receiving FIFO via the corresponding high speed serial bus, The cell stored in the FIFP is read and transmitted to the STM-1 framer 15 according to the connection information stored in the look-up table memory 25.

As described above, the APC 35 has two UTOPIA buses that are directly connected to the STM-1 framer 15 and to a plurality of transmit / receive FIFOs, when the APC 35 receives an ATM cell with UTOPIA, By using VPI / VCI (Virtual Path Indicator / Virtual Channel Indicator) and MPHY (Multiple Physical Layer) in the header of one cell, 16-bit address is used to perform 64K VC connection. At this time, the sum of the number of bits of the MPHY (two STM-1 framers and three transmit / receive FIFOs), the number of bits of the VPI, and the number of bits of the VCI should not exceed 16 bits, so it is limited to the VPI / VCI range. Will be placed.

That is, VPI / VCI that can be actually used in an ATM cell is 28 bits for NNI (Network Node Interface) and 24 bits for UNI (User Network Interface), but cannot be used.

Hereinafter, the operation of the ATM matching apparatus will be described with reference to FIGS. 1 and 2.

When a cell having a limited VPI / VCI address is received in the form of an STM-1 frame through two links from an ATM network, the STM-1 framer 15 extracts the received frame into an ATM cell and stores the received frame in an internal FIFO, followed by UTOPIA. The bus signal notifies the APC 35 that the cell has arrived, and the APC 35 receives the cell via the UTOPIA bus (URX-A). At this time, the cells received on the two links are each managed by different MPHY numbers, and if they do not violate the VPI / VCI specification range of the received MPHY port, the UTOPI bus (URX) according to the connection information stored in the look-up table memory 25. -B) is transmitted to the corresponding transmit / receive FIFO. Only cells in which the connection information exists are transmitted, and cells outside the designated range or in which the connection information does not exist are automatically discarded.

As described above, the cell transmitted to the transmit / receive FIFO according to the connection information is transmitted to the corresponding high speed serial bus under the control of the transmit / receive FIFO control unit 50 and the high speed serial bus control unit 55, and the high speed serial bus is received. The cell performs parallel-to-serial to be transmitted to the corresponding AAL processing unit.

On the contrary, the corresponding high speed serial bus receiving a cell from one AAL processor performs serial-to-parallel conversion of the received cell and transmits the cell to the corresponding transmit / receive FIFO. Here, the transmit / receive FIFO in which the cell is stored informs the transmit / receive FIFO control unit 50 and the APC 35 that the cell is received, and the APC 35 is controlled through the UTOPI bus (UTX-B) under the control of the transmit / receive FIFO control unit 50. The cell will be sent to.

The APC 35 temporarily stores the received cell in the cell buffer memory 30, and then uses a UTOPIA bus (UTX) as an MPHY corresponding to the STM-1 link number to be transmitted according to the connection information of the look-up table memory 25. -A) is transmitted to the STM-1 framer 15, and the STM-1 framer 15 converts the cell into a frame form and transmits the corresponding frame.

The VPI / VCI specification range accommodated by the APC 35 is restricted only when the APC 35 receives a cell from the network side, and there is no restriction when transmitting a cell to the network side.

As described above, in the related art, since the VPI / VCI specification range that the APC 35 can accommodate for each MPHY is allowed only from 0 to a constant VPI / VCI value, multiple access gateways are connected to one ATM network. In order to allocate VPI / VCI addresses in different areas for each gateway, service providers cannot use the high range of VPI / VCI addresses.

Therefore, the service provider cannot use the network efficiently because the network must be configured with only a limited range, and the network configuration becomes complicated.

The present invention has been made to solve the above-described problem, the VPI / VCI / of the specified range that the APC can accommodate the full-range VPI / VCI value contained in the header of the cell received at the network side It is an object of the present invention to provide an ATM matching device having a receiving cell header converting device capable of converting the VCI value to remove the limitation of the VPI / VCI specification range.

1 is a diagram showing the configuration of an ATM matching board of an access gateway matched to an ATM network.

FIG. 2 is a diagram illustrating a configuration of an ATM matching device of FIG. 1.

3 is a diagram showing the configuration of an ATM matching device having a receiving cell header conversion device according to the present invention.

4 is a diagram showing the configuration of the VPI / VCI designation range converter of FIG.

*** Explanation of symbols for the main parts of the drawing ***

100. Receive cell header converter 110. STM-1 framer,

120. VPI / VCI designated range conversion unit, 123. Transmission control unit,

125. Receive control unit, 127a, 127b. FIFO,

130.CAM, 140.APC,

200. local memory, 300. look-up table memory,

400. Cell buffer memory, 500a, 500b, 500c. Transmit and receive FIFO,

600a, 600b, 600c. High speed serial bus, 700. Transceiver FIFO control,

800. High Speed Serial Bus Controls, 900. CPU

ATM matching apparatus having a receiving cell header conversion apparatus according to the present invention for achieving the above object, extracts a frame received from the network side via a link to the ATM cell and transmits to the ATM port controller (APC) matched to UTOPIA A framer for converting an ATM cell received from the APC into a frame and transmitting the frame to a network through a corresponding link; Extract the VPI / VCI value from the header of the cell transmitted from the framer, receive the converted VPI / VCI value from the translation table memory based on the extracted VPI / VCI value, and include the VPI / VCI value included in the header of the cell. A VPI / VCI designation range converting unit for updating a VCI value with a converted VPI / VCI value provided from the conversion table memory; And an APC for transmitting the ATM cell received from the VPI / VCI designated range converter to the corresponding AAL processor based on the connection information, and directly transmitting the ATM cell received from the AAL processor to the framer according to the connection information. .

Here, the conversion table memory stores conversion VPI / VCI values corresponding to VPI / VCI values of a full range in a table form, but the conversion VPI / VCI values may be accommodated by the APC. It is characterized in that it is set to a value.

The VPI / VCI designation range converting unit extracts a VPI / VCI value from a header of a cell received from the framer, transfers the VPI / VCI value to the conversion table memory, and searches for a converted VPI / VCI value based on the VPI / VCI value. A reception control unit for updating a VPI / VCI value included in the header of the cell with a conversion VPI / VCI value provided from the conversion table memory; A FIFO corresponding to and implemented in the link and receiving and temporarily storing an ATM cell obtained by converting a VPI / VCI value from the reception control unit to the APC; When transmitting the ATM cell from the APC to the network side, a transmission control unit for generating a link selection signal for selecting a link to transmit the ATM cell under the control of the APC.

Hereinafter, with reference to the accompanying drawings will be described in detail an ATM matching device having a receiving cell header conversion apparatus according to a preferred embodiment of the present invention.

3 is a diagram illustrating a configuration of an ATM matching apparatus including a receiving cell header converting apparatus according to the present invention, a receiving cell header converting unit 100, a local memory 200, and a look-up table memory ( 300, a cell buffer memory 400, a first transmit / receive FIFO 500a, a first high speed serial bus 600a, a second transmit / receive FIFO 500b, a second high speed serial bus 600b, A third transmit / receive FIFO 500c, a third high speed serial bus 600c, a transmit / receive FIFO control unit 700, a high speed serial bus control unit 800, and a CPU 900 are provided.

In such a configuration, the local memory 200 stores application programs.

The look-up table memory 300 stores connection information for port control.

The cell buffer memory 400 is a buffer that temporarily stores cells when the APC 140 obtains port control connection information from the look-up table memory 300. After all cells are stored in the cell buffer memory 400, It is switched according to the connection information.

The transmission / reception FIFO control unit 700 controls the first transmission / reception FIFO 500a, the second transmission / reception FIFO 500b, and the third transmission / reception FIFO 500c.

The high speed serial bus controller 800 controls the first high speed serial bus 600a, the second high speed serial bus 600b, and the third high speed serial bus 600c.

The receiving cell header converter 100 includes an STM-1 framer 110, a VPI / VCI designated range converter 120, a CAM (Content Access Memory) 130, and an APC 140. The STM-1 framer 110 accommodates two STM-1 links, and when a cell is input in the form of an STM-1 frame through the link, the STM-1 framer 110 extracts the input frame into an ATM cell and matches the APC 140 with UTOPIA. In addition, the ATM cell received directly from the APC 140 is converted into a frame and transmitted to the network through the corresponding link.

The VPI / VCI designation range converting unit 120 extracts the VPI / VCI value from the header of the cell transmitted from the STM-1 framer 110 and converts the converted VPI / VCI value from the CAM 130 based on the extracted value. The VPI / VCI value is included in the header of the cell received from the STM-1 framer 110 with the converted VPI / VCI received from the CAM 130 to accommodate the VPI / VCI in the APC 140. Convert to VPI / VCI within the specified range. In the VPI / VCI designation range converting unit 120, the extracted VPI / VCI value is the VPI / VCI of the full designation range (Full-Range) sent from the network side.

The CAM 130 stores a conversion table. The conversion table is registered through the CPU bus under the control of the CPU 900. The converted VPI / VCI value is set to a value acceptable to the APC 140. It is. When the CAM 130 receives the VPI / VCI value from the VPI / VCI designated range converter 120, the CAM 130 extracts the converted VPI / VCI value corresponding to the received VPI / VCI value and converts the VPI / VCI designated range converter. Provided at 120.

The APC 140 stores the port control connection information received from the CPU 900 in the look-up table memory 300, and the network side through the STM-1 framer 110 and the VPI / VCI designation range converting unit 120. Based on the connection information stored in the look-up table memory (300), the cell received from the cell is transferred to the corresponding AAL processor via the corresponding transmit / receive FIFO and the high-speed serial bus, and the cell sent from the specific AAL processor sends the corresponding high-speed serial bus. When stored in the transmission / reception FIFO through the cell, the cell stored in the transmission / reception FIFP is read and transmitted to the STM-1 framer 110 according to the connection information stored in the look-up table memory 300.

FIG. 4 is a road showing the configuration of the VPI / VCI designation range converting unit 120 of FIG. 3, a transmission control unit 123, a reception control unit 125, a first FIFO 127a, and a second FIFO 127b. It is done by

In such a configuration, the transmission control unit 123 selects one link from two links (STM-1 link1, STM-1 link2) under the control of the APC 140 when transmitting a cell to the network side. Generate a link select signal. However, if a signal for selecting one of two STM-1 links (STM-1 link 1 and STM-1 link 2) among the transmission signals is supported at the framer stage, the transmission control unit 123 as described above may be used. It is not necessary.

The reception control unit 125 is designed as a field-programmable gate array (FPGA), extracts a VPI / VCI value from a cell header of cell data received from the STM-1 framer 110, and extracts the extracted VPI / VCI value from the MQ. [0:27] is transmitted to the CAM 130, and the VPI / VCI value included in the header of the cell received from the STM-1 framer 110 is a converted VPI / VCI value received from the CAM 130. Update

The first FIFO 127a receives and stores a cell (a VPI / VCI value converted cell) received from the reception controller 125 through the STM-1 link1.

The second FIFO 127b receives and stores a cell (a VPI / VCI value converted cell) received from the reception controller 125 through the STM-1 link2.

In the present embodiment, the first FIFO 127a and the second FIFO 127b are implemented in the VPI / VCI designation range converting unit 120. However, the first FIFO 127a and the second FIFO 127b may be implemented using an external FIFO.

Hereinafter, an operation of an ATM matching device including a reception cell header conversion device according to the present invention will be described with reference to FIGS. 3 and 4.

When the STM-1 framer 110 receives a cell in an STM-1 frame form from one link (hereinafter referred to as 'STM-1 link1'), the STM-1 framer 110 transmits the received frame to the UTOPIA bus. The cell holding state signal RCA1 indicating that there is a cell received from the STM-1 link1 is enabled and applied to the reception controller 125.

As described above, the reception controller 125 that is notified that the cell has been received by the STM-1 framer 110 by receiving the enabled cell holding state signal RCA1 from the STM-1 framer 110 may read the lead enable signal. The STM-1 framer 110, which has (RDEN1 *) enabled and applied to the STM-1 framer 110 and receives the lead enable signal RDEN1 * enabled from the reception controller 125, starts the cell. The cell data RD [0:15] stored in the internal FIFO is transmitted to the reception controller 125 together with the cell start signal RSOC1 indicating.

When the reception control unit 125 receives the cell start signal RSOC1 from the STM-1 framer 110, the reception controller 125 recognizes that it is the first word of the cell, and receives the cell data RD [0:15 that is input after the cell start signal RSOC1. Extracting the cell head's VPI / VCI value while shifting the Here, the extracted VPI / VCI value is the full-range VPI / VCI sent from the network side, and when the network interface is UNI, the extracted VPI / VCI is the MQ data format (MQ [0:27]). The VPI / VCI is converted into the MQ data format (MQ [0:31]) and sent to the CAM 130 when the network interface is NNI.

As described above, when the network interface is UNI, the converted MQ data (MQ [0:27]) has a total of 28 bytes. The VCI values are 0 to 15 bits, and the 16 to 23 bits are used. The VPI value is set to the MPHY value (for example, 4 for the first link and 5 for the second link) from bits 24 to 27.

When the network interface is NNI, the converted MQ data (MQ [0:31]) has a total of 32 bytes. The VCI value is 0 to 15 bits, and the VPI value is 16 to 27 bits. Bits 28 through 31 set the MPHY value.

Hereinafter, in the embodiment of the present invention will be described only when the network interface is UNI.

The above-described MQ data bus which transfers the MQ data MQ [0; 27] to the CAM 130 is bidirectional, the input control signal G * is high on input, and low on output. It is controlled in a low state and is applied to the CAM 130. In addition, when the MQ data MQ [0; 27] is input to the CAM 130, the SM (Start Match) signal SM * is controlled to be low so that the CAM 130 controls the MQ data MQ [0; 27]. ]) Is entered.

As described above, the CAM 130 receiving the MQ data MQ [0:27] together with the input control signal G * and the SM signal SM * in the low state is the SM signal SM * in the low state. ) Is converted from the VPI / VCI value corresponding to the VPI / VCI value included in the MQ data (MQ [0; 27]) authorized from the reception control unit 125 within a predetermined time (for example, 8 clock signals) from the time when the signal is applied. Converted VPI / VCI value extracted VCI (VPI / VCI acceptable to APC) and extracted VPI / VCI value included in MQ data (MQ [0; 27]) authorized from the reception control unit 125 It is updated to provide to the reception control unit 125. At this time, the CAM 130 applies the MQ data MQ [0; 27] to the reception controller 125 together with the MC signal MC * and the match successful signal MS * in the low state.

That is, the reception controller 125 receives the MC signal MC * and the MS signal MS * in the low state from the CAM 130, and the MC signal MC * and the MS signal MS * in the low state are applied. The time point at which the MQ data (MQ [0:27]) including the converted VPI / VCI value is applied from the CAM 130 is recognized, and the MQ data (MQ [0:27) received from the CAM 130 is recognized. ]) Updates the converted VPI / VCI value to the original VPI / VCI location of the cell that is still shifted internally.

Subsequently, the reception controller 125 controls the write enable signal WE1 * and the write control signal WC1 to be applied to the first FIFO 127a and the cell together with the cell start signal WSOC indicating the start of the cell. Data WD [0:15] is transmitted to the first FIFO 127a.

If the above-described cell data WD [0:15] is a cell received through the STM-1 link 2, the write enable signal WE2 * and the write control signal WC2 are controlled to control the second FIFO 127b. Store in

As described above, the first FIFO 127a receiving the cell from the reception controller 125 applies the enabled PF signal PF1 to the reception controller 125 so that the APC 140 reads the cell.

That is, the reception controller 125 receiving the enabled PF signal PF1 from the first FIFO 127a notifies the APC 140 of the cell holding status signal RCLAV to indicate that the first FIFO 127a has a cell. ) Is enabled and the APC 140 receiving the cell holding status signal RCLAV enabled from the reception control unit 125 enables the read enable signal RXEN * to the reception control unit 125. At the same time, the address data RADDR [0: 4] including the MPHY address (4 for the first FIFO and 5 for the second FIFO) indicating the FIFO in which the cell to be read is stored is applied.

The reception control unit 125, which has received the read enable signal RXEN * enabled from the APC 140 and the address data RADDR [0: 4], receives a read enable signal RE1 * from the first FIFO 127a. ) Is enabled and the first FIFO 127a receiving the enable enable signal RE1 * enabled from the reception controller 125 receives the cell data (RSOC) together with the cell start signal RSOC indicating the start of the cell. RXD [0:15]) is sent to the APC 140.

On the other hand, when there is a cell that the APC 140 wants to receive and transmit to the network side from the corresponding AAL processing unit through the corresponding high speed serial bus and the transmit / receive FIFO, the APC 140 transmits the cell through the STM-1 link1. APC 140 sets the value of address data (TADDR [0: 4]) indicating a link to transmit a cell to 4, and then with the enabled transmit enable signal TXEN *. It applies to the transmission control part 123.

The transmission control unit 123 receiving the address data TADDR [0: 4] together with the transmit enable signal TXEN * enabled from the APC 140 enables the write enable signal TWEN1 * to STM. -1 is applied to the framer 110 to transmit the cell over the STM-1 link1.

That is, the STM-1 framer 110 receiving the write enable signal TWEN1 * enabled from the transmission control unit 123 receives the cell holding state signal TCA1 according to the holding state of the cell to be transmitted through the STM-1 link1. ) Is enabled and applied to the transmission control unit 123, and the transmission control unit 123, which has received the cell holding state signal TCA1 enabled from the STM-1 framer 110, transmits the transmission cell holding state signal TCLAV. Enable to apply to APC 140.

As described above, the APC 140 receiving the enabled transmission cell holding status signal TCLAV from the transmission control unit 123 transmits the cell data TXD [0: together with the cell start signal TSOC indicating the start of the cell. 15]) directly to the STM-1 framer 110.

STM- which has received the cell enable signal TSOC from the APC 140 together with the cell start signal TSOC from the APC 140 after applying the enabled write enable signal TWEN1 * to the transmission control unit 123. 1 Framer 110 converts a cell received from APC 140 into a frame and transmits it to the network through STM-1 link1.

The ATM matching device including the reception cell header conversion device of the present invention is not limited to the above-described embodiment, and can be implemented in various modifications within the range permitted by the technical idea of the present invention.

According to the ATM matching device including the reception cell header conversion device of the present invention as described above, the APC accepts the full-range VPI / VCI value included in the header of the cell received at the network side. By converting the VPI / VCI value of the designated range to the APC, it is possible to support the full range of VPI / VCI required on the network side. Accordingly, it is possible to efficiently allocate VPI / VCI for each region or gateway, and even if the VPI / VCI value is assigned to a high value, all can be accommodated so that network configuration and network management can be efficiently operated.

Claims (5)

A framer for extracting a frame received from the network side through the link to an ATM cell and transmitting the frame to an ATM port controller (APC) matched with UTOPIA, converting the ATM cell received from the APC into a frame, and transmitting the frame to the network side through the corresponding link; Extract the VPI / VCI value from the header of the cell transmitted from the framer, receive the converted VPI / VCI value from the translation table memory based on the extracted VPI / VCI value, and include the VPI / VCI value included in the header of the cell. A VPI / VCI designation range converting unit for updating a VCI value with a converted VPI / VCI value provided from the conversion table memory; And an APC for transmitting the ATM cell received from the VPI / VCI designated range conversion unit to the corresponding AAL processor based on the connection information, and directly transmitting the ATM cell received from the AAL processor to the framer according to the connection information. An AT matching device comprising a receiving cell header conversion device. The method of claim 1, wherein the VPI / VCI value extracted from the header of the cell received from the framer, AMT matching device having a receiving cell header converting device, characterized in that the VPI / VCI value of the entire specified range sent from the network side. The method of claim 1, wherein the conversion table memory, Store the converted VPI / VCI values corresponding to the full-range VPI / VCI values in the form of a table, wherein the converted VPI / VCI values are set to a value acceptable to the APC. An AT matching device comprising a receiving cell header conversion device. The VPI / VCI designation range converting unit according to claim 1, The VPI / VCI value is extracted from the header of the cell received from the framer and transferred to the conversion table memory, and the converted VPI / VCI / VCI value provided from the conversion table memory retrieved the conversion VPI / VCI value based on the VPI / VCI value. A reception control unit for updating a VPI / VCI value included in a header of the cell with a VCI value; And a FIFO for receiving and temporarily storing an ATM cell having a VPI / VCI value converted from the reception control unit corresponding to the link and transmitting the same to the APC. Timing matching device. The transmission control apparatus of claim 4, further comprising a transmission control unit for generating a link selection signal for selecting a link for transmitting the ATM cell under the control of the APC when transmitting the ATM cell from the APC to the network side. An AT matching device comprising a cell header conversion device.