SU1584084A2 - Digital filter - Google Patents

Abstract

The invention relates to computing and can be used in seismic processing systems, video and other signals. The purpose of the invention is to expand the functionality by performing recursive filtering. The digital filter (FC) contains K / 2 registers 1.1 ... 1.K / 2 of the first group, K multipliers 2.1 ... 2.K, K / 2 adders 3.1 ... 3.K / 2 of the second group, K / 2 registers 5.1 ... 5.K / 2 of the second group, K / 2 registers 6.1 ... 6.K / 2 of the third group, synchronization unit 7. Recording information in the registers 1.I, 5.I and 6.I, as well as in the trigger of block 7, is carried out on the leading edge of clock pulses. Information transfer to the input of the registers 5.I and 6I is carried out by applying a low level signal to the corresponding control inputs. Block 7 operates in two modes, the modes are set by high and low signals. In each device operation cycle in non-recursive filtering mode, equal to the response time of two adders 3 and one multiplier 2, a new input sample is fed to the first information input. At the outputs of registers 1.I and 5.I, the information changes at the end of each clock cycle of the DF. The first 3.K / 2-1 cycles of operation of the FF in this mode are "idle", since The calculation of the "full" output samples begins after the appearance of the first input sample at the output of registers 1. К / 2. 1 п.з. f-ly, 4 ill.

Description

The invention relates to computing, can be used in processing systems for seismic, acoustic, video and other signals and is an improvement on the digital filter by author. No. 1314352.

The purpose of the invention is the extension of functionality due to the implementation of recursive filtering.

FIG. 1 - 3 shows the electrical structure of the digital filter; in fig. 4 - timing diagrams explaining the operation of the synchronization block in the recursive filtering mode.

The digital filter contains К / 2 registers 1.1, 1.2, ... 1. К / 2 of the first group, К multipliers 2.1, 2,2, ..., 20 2 "К, К / 2 adders 3.1,3.2, ... Z.K./2 of the first group, К / 2 of adders 4.1, 4 “2, ..., 4.К / 2 of the second group, К / 2 of registers 5.1, 5.2, ..., 5.К / 2 of the second group , К / 2 of registers 6.1,6.2, ..., 25 6, К / 2 of the third group, synchronization unit 7, first information input 8, output 9, second information input 10, control input 11.

The synchronization unit 7 contains the OR element 12, the trigger 13, the first 14 and the second 15 NAND elements, and the generator 16 clock pulses.

It is assumed that the recording of information in the registers 1.1, 5.1, 6.1, and also in the trigger 13 is carried out on the leading edge of clock pulses. The second mode of operation of block 7, as well as the inclusion, i.e. The transfer of information to the output of registers 5.1, 6.1 is carried out by applying a low level signal to the corresponding control inputs.

Block 7 operates in two modes. The first mode of block 7 is set by applying a high level signal 45 to control input 11. In this mode, a high level signal is set at the first and second outputs of block 7, a low level signal is set at the fourth output, and a sync pulse is transmitted to the third output of block 7 at each step. This is ensured by the fact that the high level signal, which is fed to the input 11, through the OR element 12, enters the D input of the trigger 13, where it is recorded at each step of the device operation.

In this case, the logical 1 signal from the direct output of the trigger 13 enters

to the second output of block 7 and to the first input of the first element AND-NOT 14, allowing the transmission of clock pulses arriving from the inverse output of the generator 16 to the third output of block 7. The logical signal O from the inverse output of trigger 13 goes to the fourth output of block 7 and to the first the input of the second element is NOT 15. This blocks the output of clock pulses to the first output of block 7, which ensures that a high level signal is set at this output,

In the second mode of operation of block 7, which is set by applying a low level signal to input 11, at the first output of block 7, the clock pulses appear at 2.4, 6, ... device cycles, and the second output sets the signal at the third output, the sync pulses appear at 1, 3, 5, ... ticks of the device, while at the fourth output a low level signal is set at these ticks. This is ensured by the fact that the logic level O at the first input of the element OR 12 provides for the transmission of a signal from the inverse output of the trigger 13 to its D input, which ensures the counting mode of operation of the trigger 13.

The clock in which the signal at input 11 changes from a high level to a low occurs is the first cycle of operation of block 7 in this mode. Therefore, in the cycles 1, 3, 5, ..., the forward output of the trigger 13 is set to a high level signal, which is fed to the second output of block 7, and also enables the transmission of clock pulses from the inverse output of the generator 16 through the first AND 14 element to the third output of block 7. In cycles 2,4,6, ... the high level signal is set at the inverse output of flip-flop 13, which causes it to appear at the fourth output of block 7, and also allows the clock pulses from the inverse output of generator 16 to be transmitted in these cycles the second element AND-NOT 15 to the first exit b Lock 7.

Registers 5.1, 5.2, ..., К / 2 of the second and 6.1, 6.2, ..., 6. К / 2 of the third group have the output control inputs. When a high level signal is applied to the control input of such a register, a high impedance state is established at its output, i.e. register

disabled. This allows the outputs of these registers to be combined.

When implementing a non-recursive digital filtering procedure, a device must evaluate an expression of the form:

y (n) -ico (i) x (n-i-H), (1)

/ where uu (i) - impulse coefficients

digital filter characteristics;

x (i) - input samples; y (n) - output counts;

K - the number of coefficients of the impulse response of the digital non-recursive filter.

Expression (1) can be rewritten as, Kg

y (n) (2j-1) x (n-2j + 2) +

) x (n-2jtO. (2)

When the device operates in non-recursive filtering mode, a high level signal is applied to input 11, which ensures the first mode of operation of block 7. In this mode, the registers 6.1, 6.2, ..., 6.К / 2 of the third group are turned off by a high level signal to the control inputs, and registers 5.1, 5.2, ..., 5.K / 2 of the second group are included.

At the synchronization inputs of the registers 5.1, 5.2, .. ,, 5.К / 2 in each clock cycle of the device receives the clock pulses. The second information input 10 in this mode receives a zero level signal. In each step of the digital filter in non-recursive mode

5840846

Consider the example of a digital filter for the case.

The clock counts at the inputs of registers 1.2 and 1.3 receive input samples x (2) and x (3), respectively. In multipliers 2.5 and 2.6, the products (2) o) (5), x (1) tt (6) are formed and summed on the adder 3.3 of the first group and JQ are fed to the second input of the adder 4.3.

In the fourth cycle, partial register is entered in register 5.3 of the second group. output countdown

15 y (6) (1) w (6) + x (2M5).

In the same cycle, the inputs of the registers 1,1s 1.2 and 1.3 receive input samples x (4), x (3) and x (2), respectively. The multipliers 2.5 and 2.6 form the products (3) n; (5) and x (2) a- (6), respectively, which are added to the adder 3.2 and fed to the second input of the adder 4.2, the first input of which is from the register 5.3 post25 in (6) ,,.

In the fifth tact in registers 5.3 and 5.2

partial output counts of y (7), x (3) and / (5) + x (2) and; (6) and y (6), x (3) and K4) + x (4) w (3) respectively are recorded . In the same cycle, the inputs of registers 1.1, 1.2 and 1.3 receive input samples x (5), x (4) and x (3), respectively. In multipliers 2.5 and 2.6, products (4) o (5) and x (3) sh (6) are formed. respectively, which are summed in adder 3.3 and fed to the second input of adder 4.3.

In multipliers 2.3 and 2.4, the products x (5) w (3) and x (4) w (4) are formed

filtering time, equal to the working time, respectively, which are summarized in

the two input adders and one clever knocker, the first information input 8 is fed a new input count. At the outputs of the registers of the first 1.1 and second 5.1 groups (, K / 2), the information changes at the end of each clock cycle of the digital filter. In the first cycle of operation, countdown x (1) is sent to the first information input 8, in the second cycle x (2), etc. At the first input of the 1st multiplier, the coefficient of the impulse response ω (1) enters (, K). The first K / 2-1 cycles of operation of the digital filter in this mode are idle, since the calculation of the total output samples y (n) begins after the output of the register 1.K / 2 of the first group contains the input sample x (1) .

adder. 3.2 and the result of the summing goes to the second input of the adder 4.2 to the first input of which from the register 5.3 goes to (7). In smart45 residents x 2.1 and 2.2, the products x (6) w (1) and x (5) u) (2) are formed, which are added to the adder 3.1 and the result of the summing goes to the second input of the adder

50 4.1, at the first input of which from register 5.2 comes in (6).

In the sixth cycle of the device operation, the partial output count, y (8), (x (3) w (6) +

55 + x (4) o (5), into the register 5.2 y (7) tx (4M4) + x (5) u (3) + y (7), (4) w (4) + + x (5) w (3) + x (2) w (6) + x (3) w (5), from the register 5.1 the first full output count y (6) y (6) g + x (5) KK2) is entered +

respectively, which are summed up in

adder. 3.2 and the result of the summing goes to the second input of the adder 4.2 to the first input of which from the register 5.3 goes to (7). In multipliers 2.1 and 2.2, the products x (6) w (1) and x (5) u) (2) are formed, respectively, which are added to the adder 3.1 and the result of the summation goes to the second input of the adder

4.1, at the first input of which from register 5.2 comes in (6).

In the sixth cycle of the device operation, the partial output count, y (8), (x (3) w (6) +

+ x (4) o (5), into the register 5.2 y (7) tx (4M4) + x (5) u (3) + y (7), (4) w (4) + + x (5) w (3) + x (2) w (6) + x (3) w (5), from register 5.1, the first full output sample y (6) y (6) g + x (5) KK2) is entered +

+ x ((1) w (6) + x (2) w (5) + x (3) uX4) +

+ x (4) uX3) + x (5) uX2) + x (6) uXO, which goes to output 9 of the digital filter. Each subsequent cycle of operation of the device at output 9 is fixed to a new output count.

When implementing the procedure recursive (oh digital filtering device must evaluate an expression of the form:

y (n) -Zu (i) x (n-i + 1) (i) y (n-i-M)

Ui

where w (i) and h (i) are the coefficients of the impulse response. When the device operates in resistive filtering mode, a low level signal is applied to input 11, which ensures the second mode of operation of unit 7. In this mode of operation, registers 6.1, 6.2, ..., 6.К / 2 are switched to the corresponding control inputs low level signal in 2,4,6 ... clock cycles of the device operation and sync pulses are received at their clock inputs in these clock cycles. Registers 5.2,5.3, ..., 5.К / 2 are turned on by applying to the control inputs a low level signal in 1, 3, 5, ... cycles of operation of the device and Synchronization pulses are received at their synchronization inputs in these taxes.

At the beginning of the operation of the device, all registers are set to the zero state (the setting circuits to the zero state are not shown).

Input samples in this mode are fed to the second information input 10 of the digital filter. In this case, the first information input 8 is turned off. In the cycles 2,4,6 .... the second information input 10 receives, respectively, the readings x (1), x (2), ..., and in the cycles 1,3,5, ... the counting arrives, equal to zero. The first information input 8 is disabled as well. To the second input of the multiplier 2.1, the information comes from the output of register 6.1, which in this mode is in the on state. In the registers of the first 1.i and second 5.i groups, the information changes at the end of each odd clock, and in the 6D registers of the third group - at the end of each even clock cycle of the device. At the first input of the multiplier 2.1 (, K) in the odd clock cycle, the coefficient of the impulse response of the digital filter, Ы (1), and in the even clock h (l), and at the first input of the first multiplier 2.1 in the even clock post0

5 0 5 0

five

0 5 Q $

is the zero operand (h (1) 0). The first 2K cycles of operation of the device are idle, since the calculation of the total output samples y (n) begins after the sum x (1) h (2) -toc (2) appears at the output of register 1.K / 2.

Example. Let be .

In the first cycle of operation of the device, the operation mode is switched and all registers are set to the initial state.

In the second cycle, the second information input 10 receives an input count x (1), which is fixed at the end of the first cycle in register 6.2. In the third cycle, due to the absence of information in the registers, the state of the circuit does not change.

In the fourth clock cycle, the second information input 10 receives an input count x (2), which is fixed at the end of this clock in register 6.2. In this case, the count x (1) is summed with the zero operand on the adder 4.1 and the result at the end of the clock is fixed in register 6.1.

In the fifth cycle, on the multiplier 2.1, the product x (1) and (1) y (1) is formed, which through adders 3.1 and 4.1 is fed to the input of register 5.1. In register 5.1, at the end of the fifth cycle, the first incomplete output count, y (1), is recorded. The count x (1) at the end of this clock cycle is fixed in register 1.1.

In the sixth cycle, the second information input 10 receives an input count x (3). In this cycle, the multipliers x 2.1, 2.2, and 2.3 form the products (1) 0,, x (t) h (2) and x (1) h (3), respectively. The first two products are summed in adder 3.1. and the result of the summing goes to the second input of the adder 4.1, where it is summed with the input sample x (2), which comes from the output of register 6.2. The sum received on the adder is x (1) b (2) - + oc (2) A1, fixed at the end of this clock cycle on register 6.1. The product x (1) h (3) through the adder 3.2 enters the second input of the adder 4.2, where it is summed with the input operand x (3). The result of the summation is fixed at the end of the sixth clock cycle on register 6.2.

In the seventh cycle on the multiplier 2.1, the product A, UX1) is formed, and on the multiplier 2.2 and 2.3, respectively, the product x (1) w (2) and x (1) tu (3). About

A (1) and (1) o (2) are summed on adder 3.1 and the result of the sum is fed to the second input of adder 4.1, where it is added to the zero one rand and the result of the sum is

A, uKl) + x (1) w (2) x (2) w (1) + x (l) W (2) + + y (1) h (2) y (2),

At the end of the seventh clock cycle is fixed in register 5.1. At the end of this clock cycle, in register 5.2, the product of x (1) and (3) is fixed. The sum (1) h (2) + x (2) at the end of the seventh cycle is fixed in register 1.1, and the input count x (1) is in register 1.2.

In the eighth cycle, the second information input 10 receives an input count x (4). In this cycle, multipliers x 2.1 - 2.4 form the products, A1h (2),), x (1) h (4), respectively. The first two products are summed at adder 3.1 and the result of the sum is fed to the second input of adder 4.1, where it is summed with the operand x (1) h (3) + x (3), coming from the output of register 6.2. The sum received on adder 4.1, equal to A1h (2) + x (1) h (3) + x (3) A2, is fixed at the end of the eighth clock cycle on register 6.1. Products A, h (3) and x (1) h (4) are added together on adder 3.2

In the eleventh cycle, the second information input 10 receives an input count equal to zero, as in all odd cycles. In this cycle, the multipliers x 2.1 ± 2.4 form the products AeoCO, Aghi (2), (3) and A1W (4), respectively. Product) (1) and Ago / (2) are summed on adder 3.1 and the result of sum is fed to the second input of adder 4.1, where it is summed with operand A (o (3) + x (1) ((4) received from register output 5.2 On the adder 4.1 in this step the first full is formed

40

and the result of the sum comes in

to the second input of the adder 4.2, where the output count

It is matched with an input x (4). Sum- y (A) -A3a, (1) + A1ft / (2) + AfW (3) + x1wU).

ma A1h (3) + x (1) h (4) -bx (4), which is obtained at the end of the measure is fixed

on adder 4.2, fixed at the end

the eighth cycle on the register 6.2.

In the ninth cycle per multiplier xx2 x 2.4, the products A2w (l), A1W (2), A, u (3) and x (1) w (4) are formed respectively. The products of Agyu (1) and Atw (2) are summed on adder 3.1 and the result of the sum is fed to the second input of adder 4.1, where it is summed with the operand x (T) w (3) coming from the output of register 5.2. Summation result equal to x (1) W (3) +

45

in the register 5.1. At the end of the eleventh cycle, in register 5.2 the sum of the products (3) and A (o; (4)) was fixed. The sum A e at the end of this cycle was fixed in register 1.1, and A - in register 1.2.

At the end of each subsequent odd clock, register 5.1 records a new output count. I

Claims (2)

1. Digital filter auth. St. No. 1314352, characterized in that, in order to expand the functional capabilities by performing recursive filtering, K / 2 registers of the third group are entered, the input and output of the first of which, with the exception of the first register of this group, are connected to the input and 1st register output five 0 five 0 count x (5). In this cycle, multipliers 2.1 ± 2.4 form the products Ai-0, Ajh (2), A4h (3), A1h (4). The first two products are summed at adder 3.1 and the result of the sum is fed to the second input of adder 4.1, where it is summed with operand A1h (3) + x (1) h (4) + x (4) received from register output 6.2. The sum received on adder 4.1, equal to A2h (2) + + A, h (3) + x (1) h (4) + x (4), is fixed at the end of the tenth cycle in register i 6.1. The products A2h (3) and A, h (4) are summed at adder 3.2 and the result of the sum is fed to the second input of adder 4.2, where it is summed with the input sample x (5). The sum AJi (3) + + A1h (4) + x (5), obtained on adder 4.2, is fixed at the end of the tenth clock cycle on register 6.2. In the eleventh cycle, the second information input 10 receives an input count equal to zero, as in all odd cycles. In this cycle, the multipliers x 2.1 ± 2.4 form the products AeoCO, Aghi (2), (3) and A1W (4), respectively. Production) (1) and Ago / (2) are summed on adder 3.1 and the result of summation is fed to the second input of adder 4.1, where it is summed with operand A (o (3) + x (1) ((4) received from register output 5.2 On the adder 4.1 in this step the first complete 5 day countdown in the register 5.1. At the end of the eleventh clock cycle, in register 5.2, the sum of the products (3) and A (o; (4)) was fixed. At the end of each subsequent odd clock cycle, register 5.1 records a new output count. I Invention Formula 1. Digital filter auth. St. No. 1314352, characterized in that, in order to expand the functionality by performing - or recursive filtering, K / 2 registers of the third group are entered, the input and output of the 1st one, with the exception of the first register of this group, are connected to the input and 1st register output the second group, respectively, and the synchronization unit, the input of which is the control input of the digital filter and connected to the control input of the first, fro register of the third group, whose input is connected to the output of the first adder of the second group, and the output of the first register of the third group is connected to the input of the first the first rpyn-jQ reg register, and the synchronization inputs of the third group of registers are connected to the first output of the synchronization unit, the second output of which is connected to the control inputs of the third 15 g group of registers, with the exception of control the third output of the synchronization unit is connected to the synchronization inputs of the registers of the first and second groups, the fourth 20 of the synchronization unit is connected to the control inputs of the registers of the second group. 6.1   -H wu Ј-1 A / $ G 5.1 FIG. 2 2. A filter according to claim 1, characterized in that the synchronization unit comprises an OR connected element, the first input of which is an input of the synchronization section, and a trigger, the inverse output of which is connected to the second input of the OR element, as well as the first and second AND elements NOT, the first inputs of which are connected to the direct and inverse outputs of the trigger, respectively, and the clock pulse generator, the direct and inverse outputs of which are connected to the trigger synchronization input and the second inputs of the first and second elements AND-NOT but, the synchronization unit outputs the first to the fourth are the output of the second AND-NO element, a direct output of the flip-flop, an output of first AND-NO element and inverse output flip-flop accordingly. LЈ g 3.1 T s L iroK t 12 hooks t iSroKT