SU1363249A1 - Digital filtration device - Google Patents

Abstract

The invention relates to computer technology and information measuring systems and can be used in systems for digital processing of signals, in particular images. The purpose of the invention is to improve the accuracy of the device. The goal is achieved due to the fact that the structure of the device includes adders 1, 8, a delay element. 2, groups of adders 3, 6.7, a group of delay elements 4, a group of multipliers 5 and a block of elements AND 9. 5 Il. CR D71, L 1/7. 00 o with y with yinf 11th

Description

with (i + l) -M input, the second output - with (i + 2) -th input, ,,,,. (p-1) th vkod-with p-m input, (p-1 + 1) -th output - with the first input, (p-1 + 2) -th output - with the second input, p-th output - with i -M input.

The structure of the digital filtering device is described by the expression d-1

H (ZHl-Z) H (a, (1)

Where

(-one

one )

-mn

(2)

The invention relates to computing technology and information measuring systems and can be used in systems for digital signal processing, in particular images,

The purpose of the invention is. improving the accuracy of the device.

Fig. 1 shows the Q structure of a digital filtering device; Fig, 2 -, the block diagram of the elements And; in FIG. 3, a delay element; . 4, the delay elements of the group;

Fig., 5 - time diagrams, by-IK „° lo А (

„„ All calculations in expressions (2) (i)

removing devices, „„

p tg y y n, substitution instead of variable z

The device (Fig, 1) contains the first

f v-f. / m 1-t-numbers are modulo an integer

the numbers 2-, X denotes the inverse of the element X in the ring of many

cops 4 delays, group multiply- ont g „„.

   members of the variable z over the ring

lei 5, third 6 and second 7 groups -1; d is the duration of the summers, the second adder 8, the block “a. impulse characteristics of the device; li (n) - counted impulse response scaled and rounded to integers, In this case, -2,

So that at the output of the arrangement Y (n) Xji (k) X (nk) it turns out

Arithmetic convolution is correct, it is necessary, based on the possible values of X (n) and h (n), select the appropriate module M according to the summator 1, delay element 2, the first group of adders 3, the group of elements

9 AND elements, 10 reference input, AND reference output, 12 coefficients setting inputs, 25

Block 9 elements And (figure 2) contains a p-code (p. D / 2, d is the length of the impulse response of the device) element And 13 and a group of two-input elements And 14, .30

The delay element 2 (FIG. 3) contains a group of shift registers 15, a group of elements NOT 16, a clock input 17 and a reset input 18, a DR input

razhieniyu:

Register 15 is entitled to the shift, Q, -d-th 35 information output.

When choosing a module according to (3), the result can be within

Element 4 group delay (phT, 4) contains a register 19, a group of elements NOT 20, a clock input 21 and an input 22, reset, D,, „„ „, DI Q, oco, Qp - in- 40 from O to M-1 The Number O Y (M-1) / 2 formation inputs and outputs are accordingly interpreted as positively register 19,

The clock inputs of the 21 elements of the 4 group delay, as well as their reset inputs 22 are combined.

All adders in FIG. 1 are

p-bit, multiplicand and multiplier in all multipliers 5 - p-bit words. Link blocks crossed out

number Y, and number (M + 1) /. Y is like a negative number - (M-Y). Similarly, 45 input counts and impulse response counts should be represented. The specified representation is a representation in the form of an p-bit reverse code.

The device for digital filter-slash, means the connection of p-discharge - 50 Cs works as follows, dow, t, e, the first output is connected to Before starting, the first input is made, the second output is from the second reset to delay element 2 and eye input, ,,,, pth output - from the elements of group 4 delay (Fig, 5), the input. If, in connection with a crossed out t, e, it is assumed that X (-d) X (-d + l) is a slash, there is an arrow with both X 55 (t) and (-1) 0, x2 U Oh, dl), then this 1st (l Oh, 1, 2 ,,,,) clock work means that when connected, the organization of the device begins with the arrival of the van cyclic shift to the right by (at its input 10 reference points X (l), Next, the bits, i.e. the first output is connected — there is a sequential triggering

with (i + l) -M input, the second output - with (i + 2) -th input, ,,,,. (p-1) th vkod-with p-m input, (p-1 + 1) -th output - with the first input, (p-1 + 2) -th output - with the second input, p-th output - with i -M input.

The structure of the digital filtering device is described by the expression d-1

H (ZHl-Z) H (a, (1)

Where

(-one

one )

-mn

(2)

Q

razhieniyu:

C / -1

(M-1) / 2 7, XU)

max

h (k)

(3)

O to M-1, O Number (M-1) / 2 is interpreted as positive.

When choosing a module according to (3), the result can be within

O to M-1, O Number (M-1) / 2 is interpreted as positive.

 combinational circuits from input 10 to output 11 of the device. In the process of triggering combinational circuits, no recording of information into delay elements 2 and 4 occurs. The inputs of the corresponding combinational circuits receive the values from the outputs of the delay elements recorded in them

at

(1st and second cycle (l 1, 2, ...) о В

In the case of a zero clock at the outputs of the delay elements, the values are zero after the initial reset. The information is written to the delay elements using clock pulses applied to the inputs 17 and 21 (FIG. 5) o

The device part consisting of the first adder 1 and the delay element 2 realizes the transfer function 1-Z, which is the first factor in (1) O This is equivalent to the realization of the following relation between the input X (l) and output U (l) sequences for this part of the device:

Uil) X (1) - X (l-d).

At the input 10 of the device receives the count X (l). At the output of the delay element 2 before the start of the 1st cycle there is a delayed count of -X (l-cL) o The minus sign is implemented by introducing a group of elements of HE 16.

Adder 1 produces the addition of X (l) and -X (l-d) modulo 2 -1 in time equal to the successive summation of two pairs of words. First, the incoming numbers are summed, and at the transfer output of the adder 1 a logical unit signal may appear. Since the transfer weight is 2, which coincides with the unit modulo 2 -1, the transfer output of adder 1 is associated with its transfer input. The resultant transfer is added to the result of the sum of the adder. 1 Thus, at the outputs of the sum of adder 1, we have the number and (1) X (1) - X (l-d) modulo 2 - 1, which is fed to the inputs of summers of matrices 3 of the first group.

The part of the device consisting of the m-th adder 3 and the m-th delay element 4 implements the transfer function (l-l-l) included in the second factor in (1). This is equivalent to implementing the following relationship between the input U (l) and output V (l) sequences for this part of the device:

0

0

15

V (l) U (l) + (-1) (1-1) „At the output of the delay element 4 before the start of the 1st cycle, we have the countdown V (ll) o It is transmitted to the second input of the adder 3 with the coefficient (-1) . The minus sign in the case of odd m is provided by transmitting the inverse outputs of the m-th delay element 4 (i.e., the outputs of the elements HE 20)

The multiplier 5 forms a 2p-bit d product (l). Since 2 coincides with the unit modulo

thirty

35

45

50

55

2 (, p-l)

matches 2

Mr.

therefore, to bring the resulting modulo 2-1 product, it is necessary to add to the younger p-bits the higher p-bits. This is performed by adder 6 of the third group of adders.

Adders 7 of the second group of adders add up the resulting products. The first 43 adders of the group add the first two products, then the second of the adders of the group adds the third description to the total, and so on. The transfer of the k-ro (d / 2-2) adder 7 of the second group, having a unit weight modulo 2-1, is transmitted to the transfer input of the (k + 1) -th adder of the same group.

The transfer (, d / 2-l) -ro of the adder a of the second group is added to the number obtained at its output of the sum using the second adder 8.

Block 9 of the elements AND serves to disambiguate the representation of a null modulo. This ambiguity arises because of the equality of the number 1 1 ... 1 with zero modulo 2 -1.

R times.

Block 9 replaces this number with zero, and skips the remaining numbers unchanged. Indeed, with the specified number, the output of the element And 13 is a logical zero, and the outputs of the elements of the And 14 group are also logical zeros. In other cases, the output of the element And 13 is a logical unit, and the bits of the number are passed to the outputs of the elements of the And 14 group without changes.

At output 11, we obtain the count Y (l) of the output sequence of the device for digital filtering. Thereafter, an entry is made in the delay element 2 and the delay elements 4 in the group of sample values formed in the 1st cycle at their inputs to use these values in

40

(l + lj-M cycle. This completes the first cycle of the device operation.

Claims (1)

Invention Formula A device for digital filtering, containing the first, second, and third adders, the input delay element, the first and second delay elements, the first, second and third groups of multipliers, the first, second, third and fourth groups of adders, the first, second and third groups of elements delays, with the output of the input g, whose transfer outputs are connected the first delay element is connected to the first input of the first adder, the sum output of which is connected to the first input of the 1st (, d / 2, d is the impulse response length) of the adder of the first group, the input of the i-ro delay element of the first group, the first inputs of the second and third adders, the outputs of the sum of which are connected to the inputs of the first and second delay elements, respectively, and to the first inputs of the first and (d / 2 + l) -th multipliers of the first group, respectively, the second inputs of which are the inputs of the first and (d / 2 + l, respectively) ) -th coefficients of the first device group, the input of setting the i-ro coefficient of the first group of which is the first input of the i-ro multiplier. The first group, the second input of which is connected to the output of the i-ro adder of the second group and connected to the input of the i-ro delay element of the second group, input which is connected to the first input of the i-ro multiplier of the second group and the input of the i-ro delay element of the third group, the output of which is connected to the first input of the i-ro adder of the third group, the output of which is connected to the first input of the i-ro adder whose second transfer input is connected the group whose transfer output is connected to the transfer input of the i-ro adder of the second group, the transfer output of the i-ro adder of the third group is connected to the transfer input of the i-ro adder of the third group, the second input of which is connected to the output of the i-ro adder of the first group, the transfer output which is connected to the transfer input i-ro of the adder of the first group, the output i-ro of the delay element of the first group is connected to the first input i-ro of the multiplier of the third group, the second input of which is the input of the i-ro 50 55 respectively to the output of the sum and the output of the transfer d / 2 of the adder of the fourth group, the second input of the 1st (, d / 2 + l) adder of which is connected to the output of the (1 + 1) -th adder of the fifth group, the outputs the senior and minor bits ix of the multipliers of the second and third groups are connected respectively to the first and second inputs i of the adders of the sixth and seventh groups, respectively, whose outputs are connected to the second inputs of the ix summers of the second and first groups, and the outputs of ix sums the second group coefficient of the device, the input of the i-ro factor of the third group is the second input of the i-ro multiplier of the second group, the transfer output of the first adder is connected to the transfer input of the first adder, the second input of which is connected to the input of the input delay element and is the information input of the device, the outputs of the first and second delay elements are connected to the second inputs of the second and third summers, respectively The transfer inputs to the second and third adders respectively, the transfer output and the output of the sum of the i-ro adders of the fourth group are connected respectively to the transfer input and the first input of the (i +1) -th adder of the fourth group, characterized in that precision, it includes the first, sixth and seventh groups of adders, the fourth adder and the block of elements AND, the outputs of the higher and lower order bits j-ro, d / 2 + 2) the multiplier of the first group are connected respectively to the first and second inputs j-ro adder n of the group, the output of the transfer of which connected to the transfer input of the j-ro adder of the fifth group, the output of the sum of the first adder of the fifth group is connected to the first input of the first adder of the fourth group, the transfer input of which is connected to the first input of the fourth adder and is the input of the logical zero of the device whose information output is output of the block of elements And whose inputs b are connected to the outputs of the corresponding bits of the fourth adder, the second input and 0 five respectively to the output of the sum and the output of the d / 2 nd adder of the fourth group, the second input of the 1st (, d / 2 + l) adder of which is connected to the output of the (1 + 1) -th adder of the fifth group, the outputs of the older and the lower bits ix of the multipliers of the second and third groups are connected respectively to the first and second inputs ix of adders of the sixth and seventh groups respectively, the outputs of which are connected to the second inputs of the ix adders of the second and first groups respectively, and the outputs of the ix adders of the sixth and seventh groups are connected to transfer inputs ix adder ov FIG. 2 Units of the current omcwmo X (1 g) y inverse races of the x (a) fig. 3 respectively groups. 8 sixth and seventh Editor A.Makovska Compiler A Baranov Tehred M. Dodyk Proofreader O. Kravtsov Order 6364/42. Circulation 671 Subscription VNII11I State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 FIG. FI.5