SU1583914A2 - Device for checking and diagnosing of digital devices - Google Patents

Abstract

The invention relates to instrumentation technology and can be used in setting up, monitoring and diagnosing digital devices. The aim of the invention is to expand the functionality of the device by providing control in a given time interval. The proposed structure of the device allows a logical analysis of the sequence of fronts of the input signal, recording and recognizing fourteen situations of the input signal. In this case, the device continuously monitors the reliability of the contact between the loop and the circuit under test. To display the fourteen input waveforms in the device, forced modulation of the displayed symbols is used and maximum consistency is achieved in cases of receiving signals of any length. 4 il.

Description

The invention relates to instrumentation, can be used in the adjustment, monitoring and diagnostics of digital devices and is an improvement of the known device by author. No. 1499286.

The aim of the invention is to enhance the functionality by providing control in a predetermined time interval.

FIG. I shows a functional diagram of the device; in fig. 2 is a table displaying functions solved by a device and the corresponding mnemonic of symbols; in fig. 3 - time diagram of the operation of the elements of the device at normalized input signal levels; in fig. 4 is a timing diagram of operation at non-standard input levels.

The device contains an input amplifier I, the first 2, the second 3 and the third 4 comparators, the first 5, the second 6 and the third 7 inverters, the first 8 and second 9 RS-flip-flops 10 pulses, the switching element 11, the indicator 12, the first 13, the second 14 and the third 15 elements of NAND, the fourth 1.6 and fifth 17 inverters, the first 18, the second 19, the third 20, the fourth 21, the fifth 22, the sixth 23, the seventh 24 and the eighth 25 D-thrngr, the fourth 26, the fifth 27, sixth 28, seventh 29, eighth 30, ninth 31, tenth 32, eleventh 33, twelfth 34, thirteenth 35, fourteenth 36, and so on

00

with

WITH

N)

behind

date 37, sixteenth 38 and seventeenth 39 elements AND –NE, sixth investor 40, resistor 41, device input 42, device control input 43, analog switch 44, ninth 45 and ds- with r 46 46 D-triggers, third short-circuit trigger 47, the eleventh D-flip-flop 48, analog switch 49, voltage divider 50, element AND 51, delay element 52, key 53,

The output of the input amplifier 1 is connected to the inputs of the first 5f of the second 3 and third 4 comparators. The output of the first comparator 2 is connected to the input and input inputs of the first D-flip-flop 18 and through the first inverter 5 to the S-inputs of the new RS-flip-flop 8, the second D-flip-flop 19, and the first inputs of the first NOT, The output of the second comparator 3 is connected with the first input of the third element AND-NO 5 and through the second inverter 6 with the first input of the fourth elec l and AND-NOT 26, The output of the fourth element AND-NO 26 is connected to the R input of the first short-circuit trigger 8 , sikhrovhodom third D-flip-flop 20s first input of the fifth element AND-NOT 279 and through the third inverter 7 - with sivkh rotate D-flip-flop 21, the output of the third comparator 4 is connected to the S-input of the second RS-flip-flop 9 and the second input of the fourth element AND-NOT 26, the P-input of the switching element 1 is connected to the R-inputs of the second RS-flip-flop 9s n In addition, 22 and seventh 24 V triggers are the second inputs of the first I3 and the fifth 27 NAND elements and through a resistor 41 with a single potential bus. The second input of the switchgear element 11 is connected to zero potential. The output of the fifth element AND-NOT 27 is connected via the fourth inverter 16 to the R-input of the second D-flip-flop 19,

the output of which is connected to R ™ and D-BXO-s of the first D-flip-flop 18, the output of the first AND-NE 3 element is connected via the fifth inverter 17 to the R-input of the third D-flip-flop 20, the output of which is connected to D- and R- inputs of the fourth B-flip-flop 21. The forward output of the first RS-Tpnfrepa 8 is connected to the synchronous inputs of the fifth 22 and sixth 23 D-triggers, and the inverse - from the synchronous seventh 24 and eighth 25 D-trig- Output n addition D-flip-flop 22 is connected to the D- and R-inputs of the eighth ID-flip-flop 251 output of which is connected

with peppy inputs of the sixth 2P and the seventh 29 NAND elements. The output of the seventh D-flip-flop 24 is connected to the D- and R-inputs of the sixth D-flip-flop 23, the output of which is. KJGH with the first input of the rjoM after the ole of the gt1T1 AND-NOT 30 and the second input of the sixth element AND-NOT 28, the input of the latter connects with the second one and the third 5 elect b.viiiTOb AND-HL. The output of the second element AND 14 is connected to the first input three) i. 35, second

CHUSH CnpOiO; epHHt.H I OUTPUT Els. I-HF 30 Output seventh ic epo (r p - SL 29 is connected to the first entrances of the twelfth element I – CHE 3-4, igor vhots ko.ogo connect with vb xor; oM of the third element and HL 15. Solder output of the first D- a trigger of 18 g j with an org entry of a loop of the slitsy loop of AND-NO 36, an inverse to the course of the pep D-flip-flop 18 is associated with a worm input i n fifteen gg, e.1g.s ti-ng 37, the output of which Soe with the first input of the seventeenth olemenga CH-NOT 39. The forward output of the fourth D-toigger 2I is connected to the first descent of Irs nadtsgsg on the element {G-NE Zo, and ichtsgrny - g second input of the fifteenth element AND-NOT 37. Exit element I-HE 39 is connected to the third inputs of the twelfth 3 and thirteenth 35 elements AND-NE A direct output of the RS-trigger 9 is connected to the first input of the ninth element AND-NOT 3), and the inverse i - with the first inputs of the tenth 32 and the eleventh 33 elements are NAND, the output of the twelfth element NAND 34 is connected to the second input of the 11th element NAND 33. The output of the 13th element NAND 35 is connected to the second input of the 10th element NON 32.

The first output of the hekeratooa 10 impulse is connected to the second inputs of the eighth 30.30 fourteen 36 K-E2 elements, the second output of the SO pulse generator is connected to the second inputs of the seventh 29, ninth 31 and seventeen 39 I-NE elements. The information inputs of the fifth 22 and seventh 24 D-flip-flops are connected to a single potential. The output of the ninth element AND-NOT 3 is connected via the sixth inverter 40 to the first input of the indicator 12, the second of which is connected to the output of the tenth element of the I-HC 32. The output of the eleventh element AND-NOT 33 is connected to the third input of the indicator 12, the fourth input of which is connected g output of the fourteenth element AND-NOT 36. The fifth input of the indicator 12 is connected to the output of the sixteenth element AND-NOT 38.

Device input 42 is connected to. First, the analog input of the analog kinema 44, the output of which is connected to the input of the input amplifier 1. The control input 4J3 is connected to the control input of the analog switch 44, the clock inputs of the ninth 45, tenth 46 and eleventh 48 D-flip-flops, S- input trg-ibjero RS-trigger 47 and the first input of the element And 51. The information input of the ninth D-flip-flop 45. is connected to the output of the first comparator 2, Information input of the tenth D-flip-flop, and 46 is connected to the output of the second com- paator 3. The information input of the eleventh D-trigger 48 is connected to a single unit potential. The direct output of the ninth D-flip-flop 45 is connected to the first address input of the analog switch 49, the second address input of which is connected to the output of the tenth D-flip-flop 46, the third address input is connected to the inverse output of the second RS-flip-flop 9. Direct output An eleventh D flip-flop 48 is co-connected to the analog input of the analog switch. The inverse output of the third RS flip-flop 47 is connected to the second input of the And 51 element, the output of which is connected via the delay element 52 to the input of the key 53, the second input of which is connected to the common bus.

The output of the key 53 is connected to the first input of the switching element I1 and K-bz; odes of nine 45, ten of 46 and

o

five

0

five

0

five

When the input of amplifier 1 to the monitored circuit is not connected to the output of amplifier I, the signal level is less than the threshold voltage for the comparators to operate 2-4. Comparators 2-4 serve to fix the excess of the voltage levels of the normalized ranges. For example, to test the circuits of TTL-series chips, they are: comparator 3 is triggered when the input level is exceeded, 4 V, comparator 2 - at, 4 V, comparator 4 - Uex, 0, OI + 0.05 V. The first trigger 8 serves for fixing the operation of comparators 2-4 in the case of monitoring levels of normalized amplitude. Triggers 22-25, the elements AND-NOT J4, 15.28-30 and 32-35 serve as a logical analysis of the input waveform of a normalized amplifier.

Triggers 18-21, AND-NE 13, 27, and 36-39 elements, inverters 7, 16, and 17 serve for a logical analysis of the input waveform of non-standard amplitude, trigger 9, AND-NE element 31, inverter 40 - for fixing the moment of contact loss probe with controlled circuit. The generator 10 serves to form the modulating voltage for the indicator 12 in cases where it is necessary to depict the latching of the input pulse signal of any duration. Moreover, the pulse frequency from 1erlthors f 0.5-2.0 Hz is chosen from the convenience of observation by the operator of these situations. At the first and second outputs of the generator 10, pulses are formed in the opposite phase to each other. The switching element I1 is used for the initial installation of the flip-flops.

Triggers 45 and 46 serve to fix the logic level at input 42.

eleventh 48 D-flip-flops, R-input d5 device at the end of the time interval

and the third outputs of the divider 50 women are connected respectively

the third RS flip-flop 47. The first and second inputs of the voltage divider 50 are connected respectively to the bus and the common bus. Pergy, the second

eg with the first, second and third analog inputs of the analog switch 49, the output of which is connected to the second analog input of the analog switch 44.

The input amplifier 1 serves to match the input circuits of the device with the inputs of the comparators 2-4 to protect the input circuits against overvoltage.

analysis, trigger 47 - to fix the beginning of the time interval in which the analysis of logical levels is performed, trigger 48 - to fix

50 end time interval for analysis. Analog switch 44 is closed to switch the analog signal, either from device input 42, or from switch 49 output by input signal r 43

55 control unit. The switch 49 serves to switch the logic levels from the outputs of the divider 50 (for example, 0.05-0.4; 0.4-2.4; 2.4 V) to the second analog input of the key 44.

analysis, trigger 47 - to fix the beginning of the time interval in which the analysis of logical levels is performed, trigger 48 - to fix

termination of the analysis time interval. Analog switch 44 is closed to switch the analog signal, either from device input 42, or from switch 49 output by input signal r 43

control device. The switch 49 serves to switch the logic levels from the outputs of the divider 50 (for example, 0.05-0.4; 0.4-2.4; 2.4 V) to the second analog input of the key 44.

15

The elements And 51, the element 52 of the delay, the key 53 are used to generate a signal blocking the installation of triggers.

The device works as follows.

In the initial state, before each control of the circuit, by chamyakia of the switching element 11, the POR device triggers are reset to the initial zero state. Comparators 2–4 are designed in such a way that, if the input to the chain is not connected, none of the comparators will work. If a logical zero signal is applied to the device input (for TTT,, A B), only comparator 4 is triggered. When a signal is input to a device with a level higher than the logical zero level but lower than the logical unit level, the comparators 3 and / ( for TTL U in 0.4-2.4 B). When a signal is applied to the input of a device with a logic unit level (for TTL Uftx 2.4 3), all comparators 2-4 are triggered, at the output of which unit potentials are set.

The operation of the device can be carried out in two modes: in mode A of continuous monitoring and mode B of monitoring in a given time interval. The mode is set by the signal level at control input 43.

In continuous monitoring mode A, control input 43 is supplied with a logic zero level at which trigger 47 is set to one, and the signal from device input 42 is fed through an analog switch to amplifier 1 input. The device monitors the voltage levels of the monitored circuits while the control signal is present at the input 43. In the initial state, the key 53 is closed with zero potential from the inverse output of the trigger 47 through the element 51 and the element 52 of the delay.

In the process of controlling the circuits of digital devices, the levels and forms of the input signal are possible (figure 2). Depending on the shape and amplitude, the device works as follows,

I. Unconnected input 42, loss of contact between the probe and the controlled circuit during control. Since Uw is less than the trigger levels of all comparators, their outputs

with

0

five

eight

Navlipakps zero potentials. The second RS-trkgeo 9 is set to a single state when there is a single potential at its direct output,. which arrives at the first input of the ninth element AND-NOT 31, the second input of which receives pulses from the second output of the generator 10. At the output of the sixth inverter 40, pulses are generated with the following frequency, 5-2 Hz (figozm). On the indicator 12 there is a flashing segment (dot), indicating the absence of contact. At the output of the elements AND-NOT 32 and 33 are the unit potentials, since from the inverse chimney of the trigger 9, the first inputs of the tenth 32 and the eleventh 33 elements AND-NOT receive a zero potential, and at the output of the elements 36 and 38 there are also single potentials, because the triggers 18 and 21 are set to the zero state, and from their direct outputs, the zero potentials are fed to the first inputs of the fourteenth 36 and sixteenth 38 IS-NOT elements. Thus, at the outputs of the NAND elements 32,33,36,38 unit potentials — the remaining segments of the indicator are not highlighted.

2. At the input 42 of the device receives a signal of a single potential. All comparators 2–4 are triggered, at the top of which a single potential is established (Fig. 3b, c, d). From the first output of the inverter 5, the zero potential arrives at the first input of the second element AND-NO 14, from the output of which the unit potential arrives at the first input of the thirteenth element AND-NOT 35. Since the flip-flops 18 and 21 are in the zero initial state, from their inverse outputs The inputs of the fifteenth element AND-NOT 37 receive unit potentials. At the output of the element AND-NO 37 is zero potential, and at the output of the seventeenth element AND-NO 39 is the unit potential that enters the third input of the thirteenth element AND-NO 35, the second input of which receives the unit potential from the output of the eighth element AND-NOT 30, since the trigger 23 is in the zero initial state. Since the potentials of the inputs of the IS-NOT 35 are unit potentials, the output of the IS-HE elements 35 is zero potential, which is fed to the second input of the tenth element AND-HE 32, the output of which is set to a single potential. Symbol indications About pl indicator 12 no. At the same time, from the bottom of the second compressor 3, the unit potential arrives at the first input of the third element AND-NOT 15, the second input of which also receives the potential from the output of the sixth element AND-NOT 28, since zero potentials come from the last input the outputs of the flip-flops 23 and 25, which are in the initial zero state. From the output of the third element AND-NOT 15, the zero potential arrives at the second input of the twelfth element AND-NOT 34; / uia south of the element IS-NOT 33, the first input of which contains a single switch from the inverse output of the second KS flip-flop 9. The zero potential from the twelfth eleventh element IS-NOT 33 (Fig. Zl) causes the symbol 1 to glow on the indicator /. The first 18 and fourth / H D-r shtory in the zero state, about zero potentials from their outputs determine the single potentials at the outputs of the fourteenth 36 and sixteenth 38

elements and NOT. Symbols and - do not flash. The zero potential from the direct output of flip-flop 9 causes a constant glow of the symbol a g through the elements AND-HE 31, inverter 40.

3. At the device input 42, there is a signal above the level of the loop, but below the logical unit. As And in the second case, the zero potency t from the output of the third element IS-NOT 15 ryvlyvaet the glow of the symbol K In addition, since the output of the first comparator 2 receives a zero potential, the unit potential from the output of the first inverter 5 enters the first input of the second element AND -NE 14, to the second input of which the Single Potential from the output of the sixth Element IS-HE 28 also enters, since the D-tr3 genes 23 and 25 are in the zero state. Thus, the zero potential from the output of the second element AND-NOT 14 successively through the elements IS-HE 35 and 32 causes the flashing of an additional symbol (Fig. Zl, m). The remaining segments of the indicator 12 are not highlighted, except for the constant confluence of the @ symbol, as in the previous case.

 , ten

15

4. At the input 4 of the device receives a signal of zero potential. At the outputs of the first 2 and second 3 comparators there are zero potentials, and the outputs of the third comparator 4 - a single potential. The single potential of the c-output of the first inverter 5 arrives at the first input of the second element AND-HE 14, the second input of which receives a single potential from the output of the sixth element EL-28, since B-trngherm 23 and 25 are in the zero state. The zero potential from the output of the element AND-NOT 14 is fed to the first input of the thirteenth AND-NO 35 epement, which causes the tenth element AND-NOT 32 to flash the symbol O, so the second ipurrep 9 is in the zero state, af is the potential with its inverse chimney arrives at the first input of the tenth element I-IIF 32.

The zero potential from the bottom of the second comparator 3 enters the first input of the third element AND-NOT 15, from which the unified potential enters the second year of the twelfth element AND-NOT 34. So ak P-tretger 25 in the nugge suction, then on the first the input of the I-HF 34 element arrives at a single potential, and its third input is also a single potential, since the D-flip-flops) 8 and 21 in the zero state at the output of the fifteenth element I - PG, 17 the zero potential, at the output the seventeenth element AND-NOT 39 units. / p potential. Thus, at the go-cement of the IS-HE 35 there are single poacals, and at its output it is zero, which determines the zero potential at the output of the tenth IS-HI element. The l symbol is not displayed. The remaining segments of the indicator 12 are not pygpechents, except for the symbols O and.

5. Potential change of single level to zero. In the case of indicator 12 to bold potential

70

25

thirty

35

40

45

50

five

symbols 1 and c are highlighted (the second case, and then there is a change in the symbols on the indicator 12 O and ft (the fourth case). The spontaneous characters do not appear.

6. The change of the zero level to individual, In - that i on the indicator 12, before the change of the current level, the symbols O and V are illuminated (the fourth case), and for CM i it goes

P158391

change characters to 1 and (second case).

7, Changing the potential of a single level to a non-standard: more logical zero, but less than a logical one. Before the change of potential on the indicator 12, the symbols 1 are highlighted.

and

(second case), after the shift

the potentials are displayed characters 0,

1 and (the third case).

8. Change of zero potential to non-standard: more logical zero, but less than logical one.

Before the potential change on the indicator 12, the symbols O and § are highlighted (the fourth case). After the potential change, the symbols 0.1 and (the third case) are highlighted.

9. Single positive pulse of normalized amplitude. In the initial state at the device input, the potential is zero, on the indicator 2, the symbols O are displayed.

and | (fourth case). Since the signal is zero, the third comparator 4 is triggered and the unit potential is at the output, and at the outputs of the first 2 and second 3 comparators the potentials are zero. From the output of the second inverter 6, the unit potential arrives at the first input of the fourth element IS-HE 26, from the output of the last potential zero sets the first RS flip-flop 8 to the zero state when there is zero potential at its direct output (FIG. 10). Since, after touching the probe of a controlled circuit by closing the circuit of the switching element 11, D-flip-flops J8-25 and RS-flip-flop 9 are set to the zero state, their outputs have zero potentials.

When the potential of the input signal changes from O - (positive edge of the pulse), the fifth D-flip-flop 22 is set to one state {Fig. Ze), since the first RS flip-flop 8 is set to one state by a signal from triggered comparator 2, while the zero potential is removed from the R-input of the trigger 8, since the unit potential is at the output of the comparator. On the trailing edge of the input signal, the zero potential is set at the output of the first comparator 2, and a single potential is formed at the output of the first inverter 5. At the output of the comparator 3

0

0

thirty

-

five

® 5

45

412

a zero potential is established, and a single potential remains at the exit of the third comparator 4 (Fig. 3b, b, g). The trigger 8 is set by a signal from the output of the fourth element AND-HE 26 to the zero state. By a positive signal drop from the inverse output of the trigger 8, the eighth trigger 25 is set to one state (FIG. ZH), since its D input receives a single potential from the output of the trigger 22. The unit potential from the output of the trigger 25 arrives at the first inputs of the sixth 28 and the seventh 29 elements are NOT. Since the second input of the seventh AND-NOT element 29 contains pulses from the second output of the generator 10, the inverted pulses from the output of the IS-NOT element 29 are sequentially fed through the elements AND-NOT 34 and 33 to the indicator segment 12, causing the modulated symbol 1 to glow (FIG. .Zl). Along with this, after a single positive pulse, zero potential remains at the input of the device. In this case, the device highlights additionally also the symbols O and, as in the fourth case.

10. A single negative pulse of normalized amplitude is fed to the input 42 of the device. In the initial state at the input of the device, the maximum potential is found, the symbols 1 and (second case) are highlighted on the indicator. Comparators 2-4 work and there are single potentials on their outputs. By the zero-level signal from the output of the first inverter 5, the first RS-flip-flop 8 is set to one when its potential inversion has zero potential. D-flip-flops 18-25 and RS-flip-flop 9 are set to zero. When the input potential is changed from c (negative edge of the pulse), the seventh D-flip-flop 24 is set to one (Fig. 3). On the trailing edge (O -) of the input signal at the output of the second comparator 3, a single potential is established, which through the inverter 6 and the AND-NE element 26 is fed to the R input of the first RS flip-flop. At the output of the first comparator 2, a single potential is set, which through inverter 5 sets

13

to the single state trigger 8. According to a positive differential signal from the direct output of the trigger 9, the sixth D-flip-flop 23 is set to one (Fig.Zi), so to some extent from the output of the D-flip-flop 24 a single potential to D- trigger input 23, which arrives at the first input of the eighth AND-NOT element and the second input of the sixth AND-NOT element 28. Since the second input of the AND-NOT 30 element contains pulses from the first output of the generator 10, then from the output of the AND-NOT element 30 pulses are received sequentially through the elements AND-NOT 35 and 32 on the segments in ikatora 12, retiring glow symbol O (fig.Zk). Along with this, after a single negative impulse, a unit potential remains at the input of the device. Us vsppechinai ..

There is additionally n characters in, as in the second case.

11. Alternation of a single positive n negative impulses, a packet of impulse normalized amplitudes. The switching element And open. After the positive pulse device arrives at the input, D-triggers 22 and 25 are triggered, and at the output of the seventh element AND-NOT 29 there are pulses from the second output of the generator 10. The pulses are sequentially passed through the elements AND-HE 34 and 33 to the indicator segment 12 , causing luminance modulated symbol 1, as in the ninth case. The next negative pulse then triggers the D-flip-flops 24 and 23 in succession, and the output of the eighth element AND-NOT 30 contains pulses from the first output of the generator 10. The pulses are sequentially passed through the elements AND-NOT 35 and 32 to the indicator segments 12, causing a modulated glow. O symbol Since the modulation of O and 1 symbols is caused by different phases of the same generator 10, O and 1 symbols alternately flash on the indicator. In addition, when both D flip-flops 23 and 25 are triggered to the inputs of the sixth element IS-28 28 upayut individual potentials. From the output of the P-NO 28 element to the second inputs of the second 14 and third 15 I-NOT elements, a blocking zero enters

ten

0 15

20

25

thirty

35

40

45

50

55

the potential by which the entry of zero potentials from the outputs of the AND-NOT 14 and J5 elements is prohibited. Since the D-flip-flops 18 and 21 are in the zero state, then at the output of the fifteenth element AND-NOT 37 there is a zero potential, from which unit potentials flow from the AND-HE element 39 to the third inputs of the AND-HE elements 34 and 35.

Thus, only at the second input of the thirteenth element AND-HE 35 and the first input of the twelfth element of INE 34 there are pulses, and at the remaining inputs of these AND-NOT elements there are unit potentials. Since RS trigger 9 is in the zero state, then. the zero potential from its direct output goes through the element of the InE 31, the inverter 40 to the dot indicator segment 12. The symbols V and alternately O and I are highlighted.

12. The sequence of pulses of normalized amplitude. The switching element II is closed. Verification of digital device circuits in this mode can be made after preliminary evaluation with open-com. mutated element II. Making sure, as in the eleventh case, about the arrival at the input of a sequence of pulses of normalized amplitude,. It is possible to roughly estimate the porosity of positive and negative pulses in the brightness of pulses O and 1. If the duration of the positive pulses is more negative, then the symbol I is flashing more brightly than O, and vice versa. Since all D-triggers of the device are kept in the initial zero state, the device alternately operates as in the second and fourth cases. The successive flashing of symbols 1 and O is determined by the arrival of input pulses from the output of comparator 2 sequentially through inverter 5, the elements AND 14, 35 and 32 on the segments O of indicator 12, as well as from the output of comparator 3 - successively through IS 15 elements, 34 and 33 per indicator segment 12, 13. A single negative pulse or a sequence of negative pulses of non-normalized amplitude. In the initial state of the device, the unit normalized potential, and at the outputs of the comparators 2-4 unit potentials (Fig. 4. O, P, d).

On the leading, negative edge of the input signal pulse (Fig. 4a) at the output of the comparator 2, a zero potential appears at which the output of the first inverter 5 does not; the potential potential that goes to the synchronous second input of the second D-trigger 19 Trigger 19 is set to the single state (FIG. 4e), and the unit potential from its output goes to the D input of the first D flip-flop 18. Because before the arrival of the falling edge of the pulse, the comparators 3 and 4 keep unit potentials on their outputs , then from the output of the element AND-NOT 26 enters the first input element AND-NOT 27 unit potential. On the falling edge (positive difference) of the input pulse, the signal from the output of the first comparator 2 sets the first D-flip-flop 18 to one (FIG. 4G), and the unit potential from its direct output goes to the first input of the fourteenth AND-36 element. The second input of which receives pulses from the first output of the generator 10. The pulses from the output of the NAND 36 element (Fig. Dm) cause an intermittent indication of the symbol. In addition, the zero potential from the inverse output of the D-flip-flop 18 determines a single potential at the output of the fifteenth element AND-NOT 37. The signal from the output of the AND-HE element 37 is fed to the first input of the seventeenth element AND-HE 39, to the second input of which the pulses from the second output of the generator 10. Next, the pulses from the output of the seventeenth element AND-NOT 39 arrive at the third inputs of the twelfth 34 and thirteenth 35 elements AND-NOT, from the outputs of which the pulses come through the elements AND-NOT 33 and 32 (fig.4l, to ) on indicator segments 12 causing intermittent indication tion symbols O and 1 in one clock cycle, and in another stroke symbol -. In addition, as in the previous cases, the symbol is highlighted.

14. A single positive pulse or a sequence of positive pulses of non-normalized amplitude. In the initial state, there is zero potential at the input of the device, zero potentials at the outputs of the first 2 and second 3 comparators, the third potential is absent from the third comparator 4 (fig.4a, b, c, d), and at the inputs of the fourth element IS-NE 26 is zero potential. On the leading edge of the input pulse, the third D-flip-flop 20 by the positive signal drop from the output of the fourth element IS-HE 26 is set to one (Fig. 4h). The unit potential g of the output of the third D-flip-flop 20 arrives at the D- and R-inputs of the fourth D-flip-flop 21. For the duration of the input pulse at the output of the first comparator 2 (fig.4b), the zero potential and at the outputs of the second 3 and third 4 comparators unit potentials. On the trailing edge of the input pulse, when the output potential of the second comparator 3 becomes zero potential, the output potential of the fourth element is zero potential. By a positive differential signal from the output of the third inverter 7, the fourth trigger 21 is set to one (Fig. 4i), and the unit potential from its direct output goes to the first input of the sixteenth element AND-HE 38, to the second input of which impulses come. the first output of the generator 10. The pulses from the output of the element IS-HE 38 (fign) cause intermittent indication of the symbol, in addition, the zero potential from the inverse, the output of the fourth D-flip-flop 21 determines the single potential at the output of the fifteenth element AND- NOT 37. the output of the seventeenth element AND-NOT 39 pulses arrive at the third inputs of the twelfth 34 and thirteenth 35 elements AND-NOT, from the outputs of which the pulses arrive through the elements AND-HE 33 and 32 (FIG. 4k, k) to the indicator segments 12, causing an intermittent indication characters 0y and 1 in one measure, and in another step of the symbol. In addition, as in the previous cases, the symbol in is displayed.

If in the process of controlling the circuits of digital devices a contact of the device probe is lost, then at the output of the third comparator a zero potential is set, according to which the second RS flip-flop 9 is set to one. In this case, the unit potential from the direct output of the trigger 9 enters the first input of the ninth element NAND 31, the second input of which receives impulses from

the second output of the generator 10. At the output of the sixth inverter 40, pulses are generated with a following frequency, 5-2 Hz (FIG. 3). On the indicator 12, the segment flashes (dot), indicating that there is no contact. The indication of the remaining segments of the indicator 12 is blocked by zero potential from the inverse output of the second RS flip-flop 9 through the first inputs of the tenth 32 and eleventh 33 NAND elements. The control should be repeated to ensure reliable contact of the device probe, imbued the triggers of the device

g

1mute closure of the switching element II as long as the number will not be highlighted simnol (point).

In mode B, when monitoring in a predetermined time interval, a single logic level is present in the initial state at the input 43 of the control device. In this case, the key 44 enters the signal from the output of the switch 49, which is blocked by zero g from the direct output of the one-year D-flip-flop 48. All triggers are Stopped in the zero state by the closure of the element 11. In the original Destination is the key 53 is opened by a single r | potential from the inverse output of the tripa 47 through the element 51 and the element 2 of the delay, and at the inputs zeroing

All triggers present zero level.

four

To control digital devices of a given time interval, a negative pulse is applied to the device input 43, the leading edge of which coincides with the beginning of the control time interval, and its rear edge (positive differential) with the time interval from the input 43 of the device The event arrives at the first input of the element And 51, and the zero potential from the output of the element And 51 triggers the delay | 52 of the delay. In addition, according to the signal from the input 43, the analog switch 44 connects to its output a signal from the device 42, which receives a signal from the controlled circuit of the digital device. Krmparatory 2-4 work depending on the magnitude of the potential at the input of the device, as in mode A.

ten

f5

20

25

0

five

0

five

0

five

The zero potential from the output of the element 51 is delayed by the delay element 52 in such a way that by the moment the key 53 is closed, when a single potential is set at the R-inputs of the flip-flops, the transients in amplifier 1 and the comparators 2-4 are terminated. The trigger 47 is set to one state by a signal from the input 43 of the device. The device is ready to fix the incoming signals at the input 42 and the recognition of their forms. In the future, the operation of the device is similar to mode A. At the end of the analysis time interval, the triggers 18-25 are set accordingly (mode A). At the information inputs of the ninth 45 and the tenth of the 46 D-flip-flops there are logical levels from the outputs of the sets 2 and 3, corresponding to the level of the signal from the input 42 at the end of the control time interval. On the falling edge () of the signal at input 43 of the device, the potentials of the outputs of Comparators 2 and 3 are fixed in D-three gages 45. and 46, respectively, the logic levels from the outputs of the latter arrive at the corresponding address inputs (first and second) of the analog switch 49, to which logical level and from the inverse output of the second RS-flip-flop, which fixes the presence of the device probe contact during the control interval of time. In addition, on the trailing edge () of the signal at input 43 of the device, the eleventh D-trigger 48 is set to one, and the unit potential from its direct output goes to the enable input of the switch 49. H output of the switch 49 receives the corresponding level the voltage of the voltage delt.- l 50 voltage, the value of which is determined by the combination of logical levels on the address control module 49. At the end of the np on input 43 of the device 44 switches the signal from the second analog input and the switch 49 to the input of the amplifier 1. Thus, the fixed and toichiat which was present at the moment of completion in uxcvii interrp.pl lchlliza. Input 42 is blocked until h. M: rn reset all triggers: s; i -. on when closing contacts

element P. On the indicator 12 emit-. MI are the corresponding symbols (seventeenth mode), equivalent to changing the shape of the input signal. The control time interval.

The effectiveness of the application of the proposed device in comparison with the known is expressed in expanding the functionality when monitoring digital devices in certain ways. Nominal time interval or tick. In the known device, due to the limited structure, all changes in the input signal from the moment of contact of the probe of the tested circuit to the current time of diagnosis are recorded, i.e. There is no temporal selectivity. This reduces the functionality, application area and makes it impossible to use the device when controlling dynamic processes in digital devices.

The proposed device does not have these disadvantages. Due to its structure, the device allows a logical analysis of the sequence of fronts of the input signal, fixing and recognizing 14 situations of the input signal. In addition, in the process of monitoring, the proposed device continuously monitors the reliability of the probe's contact with the circuit under test. The control results are unambiguously fixed on the indicator, excluding the generation of unreliable results. To display the 14 forms of the input signal on the simplest indicator in the device, forced modulation of the displayed symbols is used, and this achieves maximum consistency in the case of receiving pulse signals of any duration.

Claims (1)

Invention Formula Device for monitoring and diagnostics of digital devices auth.St. No. 1499286, characterized in that, in order to expand functional possibilities through the provision of n c 0 liver control in a given time interval, entered the analog key, the ninth, tenth and eleventh D-flip-flops, the third RS-flip-flop, analog switch, voltage divider, element And, the delay element, the key, and the device input is connected to the first analog input of the analog key, the output of which is connected to the input of the amplitude, the control input of the device is connected to the input of the analog key, with the clock inputs of the ninth, tenth and eleventh D-flip-flops, the S-input of the third RS-flip-flop and the first input m element And information input dev 0 0-trig, Hera. connected to the output of the first comparator, the information input of the tenth D-flip-flop is connected to the output of the second comparator, the information input of the eleventh D-flip-flop is connected to the single potential bus, the direct output of the ninth D-flip-flop is connected to the first address input of the analog switch, the second whose address input is connected to the direct output of the tenth D-flip-flop, the third address input of the analog switch is connected to the inverse output of the second RS-flip-flop, the direct output of the eleventh, D-flip-flop is connected to the enable input analog switch, the inverse output of the third RS-flip-flop is connected to the second input of the element I, the output of which is connected through the delay element to the first input of the key, the second input of which is connected to the common bus, the output of the key is connected to the first input of the switching element and the R-inputs of the ninth, the tenth and eleventh D-flip-flops, the R-input of the third RS-flip-flop, the first and second inputs of the voltage divider are connected to the power bus, respectively, and the common bus; the first, second and third voltage divider outputs are connected respectively to the first, second and third analog inputs of an analog switch, the output of which is connected to the second analog input of an analog switch. H P ah  I I LIX1T n l M  T f- iJt-.U JJ / f , t ™ .fTTT -.Ui  -, , -m SE r- “..