SU1580368A1 - Device for predicting evenness of shifter result - Google Patents

Abstract

The invention relates to computing and can be used in high-performance information processing systems. The purpose of the invention is to increase the reliability of the control device. The device contains a mask code generator 1, a group of blocks of elements AND, a group of 3, 4 elements EXCLUSIVE OR, a group of 5 switches, a block of 6 shift control bits, switches 7, 8 and an element of AND 9. The set of generator of 1 mask code, groups of 2 blocks And elements, groups 3, 4 elements 1 exclusive or, groups 5 of switches, switches 7, 8 and element 9 allow to generate a predicted byte parity code of the shifted number received on information input 10 of the device taking into account the check bits received on group 11 input s control bits device. This process is controlled by codes arriving at the inputs 12, 13 specifying the type and direction of the device shift with the lower bits of the input 14 specifying the shift code indicating the amount of shift within byte. The amount of shift in block 6 of the control bits shift is determined by the higher bits of the device input 14, indicating how many bytes the information is shifted. The resulting parity signal at the output 15 of the device comes from the output of block 6. Table 3, 1, ill.

Description

The invention relates to computing and can be used in high-performance information processing systems.

The aim of the invention is to increase the reliability of the control device.

 The drawing shows a functional diagram of the device

The device contains a mask code generator 1, a group of 2 blocks of elements AND, the first 3 and second 4 groups of elements EXCLUSIVE OR, a group of 5 switches, a block 6 of the shift of control bits, switches 7 and 8, an element of AND 9, information input 10 of the device, a group 11 inputs of the control bits of the device, inputs 12-14 of the type, direction and shift code of the device, respectively, output 15 of the control bits of the device, output 16 of the mask code generator, outputs 17 blocks of elements AND group 2, outputs 18 of the elements EXCLUSIVE OR first groups 3, out 19 switches of group 5, outputs 20 of the elements EXCLUSIVE OR of the second group 4, outputs 21 and 22 of the first 7 and second 8 switches, outputs 23 of the element AND 9, bus 24 of the zero potential of the device.

The operation of the device is considered for the case of a 64-bit code (8 bytes).

The set of 1 mask generator, a group of 2 blocks of elements AND, first 3 and second 4 groups of elements EXCLUSIVE OR, a group of 5 switches, the first 7 and second 8 switches and elements of AND 9 is intended to form the predicted parities of the shift result when performing shifts under managing the lower three bits of the shift code,

The mask code generator 1 is designed to form an eight-bit binary mask code, which allows to allocate in each byte of the device input information those bits that, when shifted under the control of the lower three bits of the shift code to the device input 14, intersect byte boundary i.e. jump to the next byte. Table 1 describes in detail the operation of the driver, 1 mask code, on the control input of which a control signal is received from input 13

.

5 0 5 o

five

about 5

Q

five

the direction and shift of the device, and the information inputs the lower three bits 142 of the input 14 of the device shift. For definiteness, the following is accepted: when performing a shift to the right, at input 13 of the direction of shift, the level of a logical unit is established, and when performing a shift to the left - the level of logical zero, regardless of the direction of shift, the code of the shift to input 14 of the device is received in the forward code.

The mask codeformer 1 can be performed in various ways: on the PESU 500PE 149 (the control and information inputs of the imaging unit 1 in this case are the address inputs of the EPROM); on the elements AND, OR, NOT, by performing the synthesis according to the truth table of the work of driver 1; on eight-input multiplexers 500 ID 164 (in -; in this case, it is more convenient to use Table 2, which shows the operation of shaper 1, taking into account its implementation on eight-input multiplexers).

A group of 2 blocks of elements And is designed to highlight by the mask code those bits in each byte of input information that must be pushed out of the byte boundary when performing a shift under the control of the lower bits of the shift code.

Each block of AND elements can be performed on eight two-input AND elements, the first input of which receives the corresponding mask code from the output 16 of the driver 1, and the second input is the corresponding bit of the corresponding byte from the information input 10 of the device.

The group of 3 elements EXCLUSIVE OR is intended to form parity bits of the nominated bits that are fed to the inputs of group 3 of the elements EXCLUSIVE OR from the outputs of group 2 of blocks of elements I.

The group of 4 elements EXCLUSIVE OR is intended for the formation of control bits of bytes when performing shifts under the control of the lower bits of the shift code. It should be noted that if the group of 11 inputs of the control bits of the device receives the check bits of bytes formed by parity, then the outputs 20, -20d of group 4 of the elements EXCLUSIVE OR form the predicted check bits for parity, and if the input 11 the check bits of bytes, formed by oddness, arrive, and at the outputs 20.-20c, the predicted values of

 WITH

check bits for oddness.

Groups 3 and 4 of the EXCLUSIVE OR elements can be implemented on the microscopic EXCLUSIVE OR-NOT / OR 500LP107 or on the twelve-input 500IE160 parity check schemes.

A group of 5 switches are designed to form a parity of 55–IS bytes from the first to the eighth bytes of bits when performing, respectively, are the predicted shift code, in block 6, the check bits are shifted in accordance with Table 3, in which the operation of the block 6 shift control bits.

It is noted that when performing logical and arithmetic shifts, the freed bits are filled with zero () when organizing parity check or units () when organizing odd parity check.

Thus formed at the outputs of block 6 control bits

The I to I bytes from the first to the eighth, respectively, are the predicted shift codes, in block 6, the check bits are shifted in accordance with Table 3, which details the operation of the check bits shift block 6.

It is noted that when performing logical and arithmetic shifts, the freed bits are filled with zero () when organizing parity check or units () when organizing odd parity check.

Thus formed at the outputs of block 6 control bits

shifts both to the right and to the left and can be performed on the 500LK117 microcircuits, which are two elements 2-3 I-2, OR-NOT / OR, and when the control inputs of the switches of group 5 of the switches of the logical zero level from the input 13 the device shift directions to the outputs 19, -198 of the switches 5, -5j are fed from their first inputs, thereby generating the predicted values of the byte check bits on a group of 4 EXCLUSIVE OR elements when performing left-shift shifts under the control of lower-order shift code bits ha, and when entering the control inputs of the switches 5 ..- 5. the level of the logical unit from the input 13 of the direction of the shift of the device to the outputs 19., - 19 switches

 WITH

5, -5j, information is provided from their second inputs, which ensures the formation of the predicted values of the check bits of the bytes on a group of 4 elements EXCLUSIVE OR when performing right shifts under the control of the lower bits of the shift code.

The check bits shift block 6 is designed to generate the predicted values of the check bits of the bytes when performing shifts under the control of the higher bits of the shift code. The information inputs of the control bits shift block 6 are received from the outputs 20., - 20g of elements 4, -4a EXCLUSIVE OR values of the pre-control parity bits of the shift result.

20

35

For the leftmost byte, the first switch 7 generates a parity of the sliding bits when performing a right shift under the control of the lower bits of the shift code, while the output 21 of switch 7 receives the output from output 18, element 3. EXCLUSIVE OR, if a cyclic shift is performed , the level of logical zero from input 24 - if a logical shift is performed, the value from output 23 of the element AND 9 - if an arithmetic shift is performed.

For the rightmost byte, the second switch 8 generates a parity of the shifted bits when performing a left shift under the control of the lower bits of the shift code, while the output 22 of the switch 8 receives the output from output 18, the element ILC SPLITTING OR - if a cyclic shift is performed, or logical zero level from input 24 - if a logical or arithmetic shift is performed.

Switches 7 and 8 can be implemented on the elements of 500 LAN 118 or 500 LAN 119. It should be noted that in the case of using the device only cyclic right shift (cyclic left shift is replaced in this case cyclic right by an additional code shift value) The introduction of switch 8 is eliminated. In this case

45

50

said result byte parities

shift when performing shifts under

the management of the lower three bits of the code, 55 it is time to continuously submit the level of the log shift. Under the influence of signals, post zero from input 24 of the device.

footers with input type 12 shift and 13

the directions of the shift, as well as under the control - Element I 9 is designed for the first input of the switch 5 & Necessity Senior

14

the entrance

14

Worldwide parity signal retractable

control bits of the parity of the shift result.

For the leftmost byte, the first switch 7 generates a parity of the slides that are moved when performing a right shift under the control of the lower bits of the shift code, while the output 21 of the switch 7 receives the output from output 18, element 3. EXCLUSIVE OR, if a cyclic shift is performed, the level of logical zero from input 24 - if a logical shift is performed, the value from output 23 of an element AND 9 - if an arithmetic shift is performed.

The second switch 8 generates for the rightmost byte a parity signal of the shifting bits when performing a left shift under the control of the lower bits of the shift code, while the output 22 of the switch 8 receives the value from output 18, element ZL DEPOSITING OR - if a cyclic shift is performed, or logical zero level from input 24 - if a logical or arithmetic shift is performed.

Switches 7 and 8 can be implemented on the elements of 500 LAN 118 or 500 LAN 119. It should be noted that in the case of using only a right-hand cyclical shift (cyclic left-shifting is replaced in this case by an additional shift amount code). m switch 8 is eliminated. In this case

on the first input of the switch 5 & the need for a parity signal retractable

units when performing an arithmetic shift to the right. This signal is equal to one only in the case when the device performs an arithmetic shift to the right by an odd number of bits of a negative number.

The device works as follows.

The operation of the device is considered by JQ in various modes using the example of the shift in it of eight bytes of input information afa2a s - a c. 19 binary bits (a direct binary code of the value of $ 010 OH is supplied to input 14 of the device).

Let the first byte - a # be the most significant and be accompanied by a parity check bit k, a

at the output of 181 elements 31, the parity 0 © 0 0 0 ± 0 (±

ABOUT

as an element

, F 0 © a

QJ and 3 Fa,

penj

H - © a,

, exit 18e 0 © OFO © 0 ©

at output1Y4 w IS a1l And de 18 element 3 $ the parity 0 © 0 © OFO © -0 ©, 3 © a, 4

 h f

The switch 7 generates the parity of the bits pushed into the high byte (when performing a logical right shift, the parity of the sliding bits is zero) by connecting the device logic level zero input 24 to the output 21 under the control of the device shift input signal 12.

Since the shift to the right is performed, the control inputs of the 5f-5g switches receive a log-eighth byte aflasia fg - au is the 20th unit, under the action of which is the youngest and is accompanied by a parity check bit k.

Shift right logical.

The parity's first information input on the outputs 19 f 9g of the switches

- -I

the nominated bits from outputs 18–187, respectively (the output of the 19T compressor 1 of the mask code receives the level 25 Mutatora 5 and the value is even30

35

The logical unit from the input 13 specifies the direction of the device to shift to the right, and the second information input of the imager 1 is supplied with the value of the lower three bits 14 of the input 14 of the device shift code (011 in the considered example). In accordance with the operation of the imaging unit 1 (Table 1), in its outputs 16, in this case, the mask code 000001 AND is formed, which is then fed to the first inputs of the blocks 2, -2c elements

And, to the second inputs of which the values of the corresponding bytes 10Т - 108 of the input information from the input 10 of the device are supplied, as a result of this, only those bits of the corresponding I0t-10g bytes 45 that are to be pushed to the outputs of blocks 21-2 of the elements byte boundary when performing shift under control of lower bits of shift code. For the case in question, at the g outputs of block 2 a masking result of 00000a, a7a is formed. at the outputs of I 74 block 2 g - OOOOOa a lfu in etc., at the outputs of $ 17 block 28 - the result of masking OOOOOAa a,

ti bit into the high byte bits from the output 21 of the switch 7).

Thus, at the inputs of elements 4-4a EXCLUSIVE OR three components are supplied: check bits

11, -110 corresponding bytes with input 1 to

yes 11 check bits of the device; the parity of the bits to be extended from these bytes from the outputs 18f-18g, respectively, and the parity of the bits to be extended from the adjacent left bytes from the outputs, respectively, are the parities of the bits to be moved in accordance with the bits. At the exits

40 elements form the predicted values of the control

byte bits when performing the shift under the control of the lower bits of the shift code. So, at the output 20 .. of element 4, a check bit of K K1 © © 0 is formed, at the exit of the 20 element K () R A Р P, etc., at the exit 20g of the element 48 - a check bit of K K8 © f. In block 6, the shift of the control bits under the action of the control signals from the input 12 sets the type of device shift, the level of the logical unit coming from the input

Further, on the basis of the results of the mapping-13 setting of the shift of the devices obtained at the outputs 17, -17 e, using the 3f-3g elements EXCLUSIVE OR the parities of nominated ъ each bit byte are formed. So,

as well as under the control of the higher bits 14., the inputs 14 of the device shift code (in the example in question, the value of the three most significant bits at the output 181 of the elements 31 is the parity 0 0 0 0 0 0 (±

ABOUT

as an element

, F 0 © a

QJ and 3 Fa,

penj

H - © a,

, exit 18e 0 © OFO © 0 ©

at output1Y4 w IS a1l And de 18 element 3 $ the parity 0 © 0 © OFO © -0 ©, 3 © a, 4

 h f

The switch 7 generates the parity of the bits pushed into the high byte (when performing a logical right shift, the parity of the sliding bits is zero) by connecting the device logic level zero input 24 to the output 21 under the control of the device shift input signal 12.

Since the shift to the right is performed, the level of the logical unit enters the control inputs of the switches 5f-5g, under the influence of which

five

50

ti bit into the high byte bits from the output 21 of the switch 7).

Thus, at the inputs of elements 4-4a EXCLUSIVE OR three components are supplied: check bits

11, -110 corresponding bytes with input 1 to

yes 11 check bits of the device; the parity of the bits to be extended from these bytes from the outputs 18f-18g, respectively, and the parity of the bits to be extended from the adjacent left bytes from the outputs, respectively, are the parities of the bits to be moved in accordance with the bits. At the exits

0 elements form the predicted values of the control

byte bits when performing the shift under the control of the lower bits of the shift code. So, at the output 20 .. of element 4, a check bit of K K1 © © 0 is formed, at the exit of the 20 element K () R A Р P, etc., at the exit 20g of the element 48 - a check bit of K K8 © f. In block 6, the shift of the control bits under the action of the control signals from the input 12 sets the type of device shift, the level of the logical unit coming from the input

as well as under the control of the higher bits 14., the inputs 14 define the device shift code (in this example, the value of the three higher bits 915

The odds is 010) the control bits shifted at the outputs 20 ,, 20j and received at the corresponding information inputs of block 6 are shifted in accordance with its operation (Table 3). The outputs of block 6 in this example are formed after

The following control bits are O, O, K, K, K3, K4, K, Ks. These control

the bits supplied to the output of the device’s 15 control bits are the predicted parities of the shifter,

The mismatch of at least one byte of the result of the shift of the values of its actual and predicted parities indicates the presence of an error either in the input information of the shifter or in its equipment.

Arithmetic right shift

In this mode, the device works like the previous one. The only difference is that the switch 7, forming the parity of the bits inserted into the high byte, connects the output 23 of the element AND 9 under the control of signals from the input 12 of the device shift type to the output 21 of the switch. In this case, at the output 23 of the element And 9 forms, with the sign P, which takes into account the parity of the units being moved when shifting the negative number (in the considered example, the sign P a, since the right unit is being shifted and the level of the logical unit arrives at the first input of the element 9 and The low-order bit 143 of the input 14 of the assignment code of the device shift, connected to the second input of the element And 9 is set to one).

In accordance with the above, at output 20., element 4, an EXCLUSIVE OR check digit is generated,

kp k. h @ p.

1 1 Right shift is cyclical.

In this mode, the device operates in the same way as the described right shift mode. The difference is that the switch 7, forming the parity of the bits inserted into the high byte, connects the I8g output of the element 3S EXCLUSIVE OR controlled by signals from the I2 input of the shift type

vani block at the outputs

17z block 2s - the result

devices to switch 21 output,

so as nominated from the younger by-55 masking assa 00000

This bit is retractable in 1 Further, based on the results

high byte bits when performing masking, received, n-i outputs

the cyclic shift to the right under the control, I71-I7g, are formed by the parity by extracting the lower bits of the shift code.

Twill with the above item 4 EXCLUSIVE

O

0

JQ OR check bit is generated.

TO

K, © P

view

© Р

view

1 |

In addition, in block 6, the shift of the control bits under the control of signals coming from the input 12 sets the type of device shift, the level of the logical unit coming from the input 13 sets the direction of the shift of the device, and also under control

senior bits 14 inputs 14 backwards "/

Neither the device shift code (in this example, the value of the three most significant bits is 010), the control bits shifted at the outputs 20f-20g and received at the corresponding information inputs of block 6 are shifted in accordance with its operation (Table 3).

In this example, the following endings are formed at the outputs of block 6

five

0

five

control points:

g PTT P7G Ltg (1

k1; to

to ,, to

5 Ke, k, K Ј and K Ј. These check bits, which are predicted by the parities of the shift result, arrive at the output of 15 check bits of the device.

Shift left logical.

The control input of the formaker 1 of the MSK code receives the logical zero level from the input 13 of the device direction setting, corresponding to the left shift, and the information inputs of the imaging unit 1 are supplied with the value of the lower three bits 14-1 inputs 14 of the device code shift (in the considered example 011). In accordance with the operation of the imaging unit 1 (Table 1), in its outputs 16, in this case, the mask code 11100000 is generated, which is then fed to the first inputs of the blocks. elements And, on the second inputs of which the values of the corresponding bytes 101-10 are applied. input inlo

formations from the input 10 of the device data. As a result of this, for

of the case at the outputs of 17 ,, block 2. the result of the mask

at the exits 17 For, „a„ IOOOO

(

vani block at the outputs

a, aza E00000

0a „00000

2 17z block 2s - the result

by the power of elements 3 „-3 EXCLUSIVE OR. So, at the output of 18, element 3, the parity of R. is formed, @ a3 @ 0 0 0 (± 0 0 0 0 0, at the output of the 8g element of гg - the parity of a. ®0 0 0 (5 O О O О O , etc., at output 18, of element 3g is the parity of P g © ayj® 0® O © 0 © 0. The switch 8 forms the parity of the bits pushed into the lower byte (when performing logical and arithmetic shifts to the left, the parity of the pushed bits The device is equal to zero), connecting the device logic level zero input 24 to output 22 under control of signals from input 12 specifying the device shift type.

Since the shift to the left is performed, the control inputs of the switches 5, -5 o receive a logic zero level, under the action of which the outputs 19t-197 of the switches 5t-57 receive the parity of the bits to be extended from the outputs, respectively (and the output 9g of the switch 5g enters the value of parity in the bits to be moved to the low byte from the output 22 of the switch 8).

Thus, the inputs of the EXCLUSIVE OR elements are received by three components: check bits 11., - llj of the corresponding bytes from the input 1 1 of the device; the parity of the bits to be extended from these bytes from the outputs JSj-lSj, respectively, and the evenness of the bits to be moved out from the neighboring right bytes from the outputs 19f-19, respectively, are the parities of the bits to be slid into the corresponding bytes. Outputs 20, -20g elements

4-4 „, the predicted values of the check bits of the bytes are formed when performing the shift under the control of the lower bits of the shift code. Thus, at output 201 of element 4, a check bit is generated to K, ® Pe, A G

+ P

6TH

at the exit 20 of the element 4 VIA

view

K Kg + P p + P, etc., at the output of 20 tons of the element 47 is the control bit of К К7 ® Р ™ © Р V, at the exit of 20, of the 4 g element - К К g © Р Ь А Ф O. В block 6 of the shift of the control bits under the action of signals coming from the input 12, specifying the device shift type, logic level 0, coming from the input 13 setting the device shift direction, as well as under the control of the higher bits 141 of the input 14 setting the shift code device

 , about

five

(in this example, the value of the upper three bits is 010) the shift of the check bits generated at the outputs 20. -20. and received at the corresponding Information inputs of block 6, in accordance with its work (Table 3). In this example, the following check bits are formed at the outputs of block 6: Kf, KЈ, KЈ, K, K, K8 °, O, O, These check bits, which are predicted by the parity of the shift result, arrive at the output of 15 check bits of the device .

Arithmetic right shift.

In this mode, the device works exactly the same as in the previous mode, and for the same data the same values of the predicted parities of the shift result are generated.

Shift left cyclical.

In this mode, the device operates in the same way as the described left-shift mode. The difference is that the switch 8, forming the parity of bits inserted into the low byte, connects the output 18 of element 3 EXCLUDING OR controlled by signals from the input 12 of the type setting — device shift to the output 22 of the switch, because the bits pushed out of the high byte are bits shifted into the lower byte when performing a left-shift cyclical under the control of the lower bits of the code shift. In accordance with the above, at output 20l of element 4, the EXCLUSIVE OR is formed the control bit Knt K, 0Р Г © Р ..

In addition, in block 6, the shift of the control bits under the control of signals coming from the input 12 specifies the device shift type, the level of logical zero coming from the input 13 specifying the device shift direction, and also under the control of the higher bits 14 of the input 14 setting the device shift code (in this example, the value of the three most significant bits is 010), the r shift of the control bits formed at the outputs 20, -20 is fulfilled. and received at the corresponding information inputs of block 6, in accordance with its work (Table 3). In this example, the following control bits are formed at the outputs of block 6: Kj,, KЈ, K /, K7P, K, K, K2- These | the control charts, which are the predicted parities of the shift result from the driver, arrive at the output of 15 test bits of the device.

Claims (1)

Invention Formula A device for predicting the parity of the shift result, comprising a mask code generator, two switches, an AND element and a group of AND blocks, the first and second inputs of the AND element are connected respectively to the low-order input of the device-shift-code setting and the high-level discharge of the information input of the device The output of the mask code generator is connected to the first input of the first block of elements AND of a group, characterized in that, in order to increase the reliability of control of the device, the switchboard group is entered into it the two groups of elements EXCLUSIVE OR and the shift block of the check bits, the input specifying the direction of the shift of the shift block of the check bits, the third input of the And element and the first information input of the mask code generator, are connected to the input of the setting of the device shift direction, byte bits of the information device inputs are connected to the second inputs of the corresponding blocks of elements AND groups, the bits of the output of the mask code generator are connected to the first inputs of the corresponding blocks of elements IGR, the output of the 1st block is The elements AND groups are connected to the corresponding input of the 1st element EXCLUSIVE OR of the first group, the output of which is connected to the first input 1st element EXCLUSIVE OR of the second group (1 4 i m, where m is the number of blocks AND in the group), the output of which is connected to the i-th information input of the block the shift of the control bits, the information output of which is the output of the control bits of the device, the output of the AND element is connected to the first information input of the first switch, the second and third information inputs of which are connected respectively to the zero potential bus of the device and the output of the last element EXCLUSIVE OR and the second information inputs of the second switch are connected respectively to the zero potential bus and the output of the first element EXCLUSIVE OR of the first group, you One of the first switch is connected to the first information input of the first switch of the group, the output of each j-ro element EXCLUSIVE OR of the first group is connected to the first information input (j + l) -ro of the switch of the group (I mj m-1), the output of each 1st element EXCLUSIVE OR of the first group is connected to the second information input (1-1) of the group switch (2 1 4t), the output of the second switch is connected to the second information input of the last switch of the group, the control bit shift type input and control inputs of the first switch and the second switch is connected to the input of the device shift type setting, the input of the device shift direction setting is connected to the control inputs of the switch groups, the outputs of which are connected to the second inputs of the corresponding EXITING OR second elements, the third inputs of which form the group of inputs of the device control bits, the lower bits of the input of the device shift setting value are connected to the second information input of the mask code generator, the senior bits of the input of the code shift code of the device connecting to the input of the code setting of the shift value of the shift block of the check bits. Note: R and R are the direct and inverse levels of the logic signal installed at the control input of the shaper 1 (at the input 13 of the device shift direction) Table I iches About (left) 000 001 010 011 100 101 ON 1 1 1 0 (left) EU 000 001 010 011 100 101 ON AND) Cyclic-1 (table 3 I2 FROM I4 I5 I6 I7 I8