SU1167655A1 - Storage with random access and simultaneous access to variable word array - Google Patents

Abstract

STORAGE DEVICE WITH ARBITRARY ACCESS AND SIMULTANEOUS SELECTION OF A VARIABLE MASSAGE OF WORDS, containing blocks of memory consisting of accumulators, the address inputs of which are connected to the outputs of the corresponding address switches of the address signals, control inputs of which are connected to the output of the shafts, and the bundles of the shafts of the switches of the address signal switches, the control inputs of which are connected to the output of the shafts of the shafts of the address switches; are the first address input of the device, others are the second address input of the device, characterized in that, in order to simplify the device, the first, second and three are entered into it The first comparison units, the first and second decoders, the first and second reverse signal conditioners and the switch resolution signal switcher, whose outputs are connected to the inversion enable inputs of the respective accumulators, and the inputs are connected respectively to the outputs of the decoders, inverter signal generators and the output of the third comparator unit, the first the inputs of the control signal generator, the first and third comparison blocks and the second reference signal generator and the inputs of the first decoder are the first the control input of the device, the second inputs of the control signal generator and the first comparison unit and the first input of the second comparison unit are the second control input of the device, the second inputs of the second and third comparison units and the second reference signal generator and the inputs of the second decoder are the third control the input of the device, the inputs of the first inverter shaper are connected to the outputs of the decoders and the third comparison unit, the third, fourth and fifth inputs of the second shaper signal Circuits are connected respectively to the outputs of the first, second and third units of comparison.

Description

The invention relates to computing, namely, random access memory devices (RAM) for computers.

The memory device containing the accumulator, the control regions for which the command is received, including the address of the address, and the information fields for which the information 1 is received and transmitted in the memory are known and transmitted.

However, the possibility of using this memory in many modern computers, in particular in multiprocessor computers, where memory with a variable access format is required, i.e. with simultaneous sampling of several words at the same call command, are limited.

The closest to the proposed is a memory with an arbitrary simultaneous sampling of a variable array of words, in which the device access command contains the main and additional addresses (in the particular case differing by one) and the address format specified, for example, in the form of initial and final bounds circulation, and which contains a control unit, a drive consisting of several sections, each in one word format, to the inputs of which is supplied the main or additional address from two-code switches and a signal s 2 resolutions Display resolution handling.

The disadvantage of this device is the high hardware costs. In addition, the device cannot be used as a module for building multi-module storage devices that differ in maximum reference format and are intended for multi-processor variable-configuration computers that use a memory access command generation unit that is uniform for all configuration options.

The purpose of the invention is to simplify the device and expand its scope by being able to be used as a module for increasing the memory format.

The goal is achieved by the fact that a random access memory device with simultaneous sampling of a variable array of words containing memory blocks consisting of accumulators whose address inputs are connected to the outputs of the corresponding address switches, the control inputs of which are connected to the output of the control generator signals, one of the information inputs is the first address input of the device, the others are the second address input of the device, the first, second and third comparison blocks are entered, ne left and second decoders, first and second reference signal conditioners, and resolution enable switch, whose outputs

connected to the access outputs of the corresponding drives, and the inputs are connected respectively to the outputs of the decipherors, the formers of the circulation signals and the output of the third comparison unit, the first inputs of the control signal generator, the first and third comparison blocks and the second signal conditioner and the inputs of the first decoder are the first control by the entrance

0, the second inputs of the control signal generator and the first comparison unit and the first input of the second comparison unit are the second control input of the device, the second inputs of the second and third comparison blocks and the second reference signal generator and the inputs of the second descrambler are the third control input of the device , the inputs of the first inverter are connected to the outputs of the decoders and the third unit of comparison, the third, fourth and fifth inputs of the second inverter are connected ootvetstvenno with outputs of the first, second and third comparator units.

The drawing shows the functional

5 diagram of a memory device with random access and simultaneous sampling of a variable array of words.

The device contains 1 memory blocks (one memory block is shown in the drawing), each of which contains accumulators 2 having address inputs 3 and access enable inputs 4. The memory unit 1 has the first 5 and second 6 address inputs, which are the address inputs of the device. Each memory block 1 contains switches 7 with control inputs 8. The control inputs of the device are inputs 9-11, respectively, which serve to signal the initial access limit, the number of the memory block and the final access boundary.

The device also contains the first comparison unit 12, which serves to compare the initial access limit with the number of memory block 1, the second comparison unit 13, which compares the final reference limit with memory number of memory 1, the first 14 and the second 15 digits, the third comparison block 16 For comparing the start and end boundaries, the first 17 and second 18 address signal conditioners, the access resolution switch 19, and the control signal generator 20. Descramblers 14 and 15 are decoders with an output spread. Unlike conventional decipherors, in propagation decoders, not one selected output bus, the number of which corresponds to the input code, but a group of output tires, starting with the selected and ending last

number. In this case, the inverse decoder is used in the decoder 15.

Consider the operation of the device for a particular case when the number of drives 2 is 16, the maximum number of memory blocks 1 forming the computer memory is 4.

At the same time, the code of the initial circulation boundary is 6-bit. We denote these bits by ao, aj, ag, aj, a, as- The code of the finite inversion boundary is also 6-bit (bits BO, Bj, Bj, Bj, b, BS). The code of the assigned drive number is 2 bits. We denote these bits by eo, ej.

For this particular case, truth tables are given for blocks 17-19. In them, the outputs of the blocks are indicated as follows. For example, the output of block 16: Ex. 16. If the output of a block is multi-digit (multi-block), it is accompanied by the designation by the number of the output band: for example. Out 17g - for the second discharge.

The truth table of the first inverter 17 is Table. I

The truth table of the second inverter 18 is Table. 2

Switch permission signal switch 19 is a conventional 4 in 1 switch and consists of four 4-bit sections. Due to the cumbersome truth table of the entire switch 19, it is made up of two truth tables of the switch control signals (Tables 3 and 4) and four separate tables for each section of the Switch 19 (Table 5-8).

The device works as follows.

At the input 10 of the device, the code but the measure of the memory block 1 is supplied. At the inputs 5, 6. 9 and 11 of the device, the address is given to the part of the call command: the main address is fed to input 5, the additional address to input 6, the code of the initial reference of the address — pa V. 9 and the code of the final limit of circulation — to input 11 (the operation code, also included in the call command, is sent to the device control unit, which is not considered in the description of the invention and is not shown in the drawing).

Blocks 12 and 13 define the equality of the codes ao, ad.seo, t and o, i with e, e, respectively. To the input of the de-bifter 14, bits of the code of the initial boundary of the FOR arrive. as the input of the decipheror 15 receives bits of the code of the final boundary in, B5.

The inputs of block 16 receive the codes a, -as and BO-BS- The output signal at its output takes the value 1 when aoajajaja aj is BoBiBjBjB Bs and the value O when this ratio is not fulfilled.

The remaining blocks operate in accordance with the above truth tables (Tables 1–8).

The technical and economic advantage of the proposed storage device is that its use allows the use of a unified memory access command generation unit that does not contain redundant equipment for all variants of computer memory configuration.

Inputs Shaper 17

Vyh.16a 35-in + I BD-I Vyh.17oVykh.17 Vyh.17g .17z

11g 11III

Table

Shaper Outputs 17

Note. An X indicates that the input status is undefined.

table 2

Table 3

Table4

Table3

Table

Claims (1)

A REMEMBERING DEVICE WITH ARBITRARY ACCESS AND SIMULTANEOUS SELECTION OF VARIABLE WORD OF WORDS, containing memory blocks, consisting of drives, address inputs of which are connected to the outputs of the corresponding switches of address signals, the control inputs of which are connected to the output of the driver, control signals, one of the information input addresses devices, others - the second address input of the device, characterized in that, in order to simplify the device, the first, second and third blocks are introduced into it comparison kiosks, the first and second decoders, the first and second shaper of the access signals and the switcher of the permission signals, the outputs of which are connected to the inputs of the permission of the corresponding drives, and the inputs are connected respectively to the outputs of the decoders, shapers of the access signals and the output of the third comparison unit, the first inputs the shaper of the control signals, the first and third blocks of comparison and the second shaper of the access signals and the inputs of the first decoder are the first control the device’s progress, the second inputs of the driver of the control signals and the first comparison unit and the first input of the second unit of comparison are the second control input of the device, the second inputs of the second and third blocks of comparison and the second driver of the access signals and the inputs of the second decoder are the third control input of the device, inputs the first signal shaper is connected to the outputs of the decoders and the third comparison unit, the third, fourth and fifth inputs of the second signal shaper are connected neny respectively with the outputs of the first, second and third blocks of comparison. SU 11676 SI SP>