SU1658155A1 - Device for shifter result parity prediction - Google Patents

Abstract

The invention relates to automation and computing and can be used in control organization in high-speed arithmetic devices. The purpose of the invention is to reduce the hardware cost of the device. The device contains a mask code generator 1, a group of 2 elements AND, a group of 3 elements of an OR element, two groups of elements EXCLUSIVE OR 4, 5, a group of switches 6, a block 7 of shift of control bits. The combination of a mask code generator 1, a group of blocks 2 elements 4, a group of blocks 3 elements OR, two groups of elements EXCLUSIVE OR 4, 5, a group of switches 6, switches 8, 9 and element 10 is intended to form the parity result of the shifter under the influence of the lower three bits Shift Code Code (by an amount less than the length of a byte). The check bits shift block 7 performs the formation of check bits under the action of the higher bits of the shift code by a multiple of a byte. 3 tab., 2 Il. And O ate 00 followed a jff

Description

The invention relates to automation and computing and can be used in control organization in high-speed arithmetic devices.

The purpose of the invention is to reduce the hardware cost of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - connection of the block of elements AND, bypass of the elements OR and the element EXCLUSIVE OR of the first group.

The device (Fig. 1) contains the shaper 1 of the mask code, the group of blocks 2 elements AND, the group of blocks 3 elements OR, the first or second groups of elements EXCLUSIVE OR 4 and 5, respectively, the group of switches 6, block 7 of the control bits shift, switches 8 and 9, element 10, information input 11 of the device, input 12 of the control bits of the device, inputs 13–15 of the direction, type and code of the device shift, respectively, output 16 of the control bits of the device, outputs 17–27 of the device nodes and blocks, and bus 28 zero potential of the device.

The combination of a mask code generator 1, a group of blocks 2 elements AND, a group of blocks 3 elements OR, the first and second groups of elements EXCLUSIVE OR 4 and 5, a group of switches 6, switches 8 and 9 and element 10 and is intended to form the parities of the result of the shifter shifts under control of the lower three bits of the Shift code.

The mask code generator 1 is designed to form a nine-bit binary mask code that allows to allocate in each byte of the device input information those bits that, when shifted under the control of the lower three bits of the shift code received at the device input 15, or cross the byte boundary i.e. go to the next byte (if the value of the three least significant bits is less than four), or remain in the given byte (if the value of the three least significant bits is greater than or equal to four), while in the second case the check bit of the byte is also selected. In tab. 1 describes the operation of the mask code generator 1, the control input of which receives the control signal from the device shift direction input 14, and the information inputs the lower three bits 152 of the device shift code input 15, For definiteness, they accept the following: the input 14 of the direction of the shift device is set to the level of logical units, and when performing

left shift - the level of logical zero; regardless of the direction of the shift, the shift code to the input 15 of the device comes in a direct code.

The mask code generator can be performed in various ways: on the PROM 500 RU149 (the control and information inputs of the imaging unit 1 in this case are the address inputs of the EPROM); on

0 elements AND, OR. NOT, performing the synthesis according to the truth table of shaper 1; on eight-input multiplexers 500 ID 164 (in this case it is more convenient to use Table 2, which shows the functionality of shaper 1, which takes into account its implementation on eight-input multiplexers).

The value of the digit of the mask code at the output of the 17d coincides with the value of the higher digit of the lower bits of the 152 input 15 of the device and. consequently, for the implementation of a formaker 1 mask code, only eight chips 500 ID 164 are required.

Group of blocks 2 elements And group

For each byte of input information, 5 blocks of 3 elements OR and the first group of elements EXCLUSIVE OR 4 form the parity of bits to be moved beyond the byte boundary when performing shifts controlled by the lower three bits of the shift code.

In the case of using odd evenness control, the third inputs of blocks 2i-2e groups should receive the inverse values5 of the corresponding check bits from the input 12 of the control bits of the device, while the third inputs of the elements EXCLUSIVE OR 5i-5a groups should be fed direct values of test bits from the input 12 of the device.

The second group of elements EXCLUSIVE OR 5 is designed to form the check bits of bytes when

5 performing shifts under the control of the lower bits of the shift code. In this case, if the input bits of the bytes, formed by parity, are input to the 12 control bits of the device, then

In the outputs of the EXCLUSIVE OR 5 group of elements, the predicted parity check bits are formed, and if input 12 bits of control bits arrive, oddly formed and even at the outputs of the EXCLUSIVE OR 5 element groups, the predicted odd bits are generated.

A group of switches 6 is designed to form parities inserted into

bytes of bits when performing shifts both to the right and to the left, and can be performed on the 500LC117 microcircuits, which are two elements 2-ZI-2, OR-NOT / OR, and when they arrive at the control inputs of the switches of the group of logical zero from the input 14, the device shift directions to the outputs of the group switches 6i-6a are supplied with information from their first inputs, thereby generating the predicted values of the check bits of the bytes on the group of EXCLUSIVE OR 5 elements when performing left-shift under the control of the lower the shift code bits, and when groups of a logic level unit from the switch inputs 6i-6s arrive at the control inputs of the switches 6i-6s, information from their second inputs is supplied to the outputs of the switch groups, which ensures the formation of the predicted values of the check bits of bytes per group of EXCLUSIVE elements OR 5 when performing right shifts under the control of the lower bits of the shift code.

Block 7 of the control bits shift is designed to generate the predicted values of the control bits of the bytes when performing shifts under the control of the higher bits of the code: scaling. The check bits of 16i-16n bytes formed from the outputs of block 7 from the first to the eighth, respectively, are the predicted check bits of the result parity shifted. The operation of the check bits shift block 7 is explained using the table. 3

For the leftmost byte, the first switch 8 generates a parity of the sliding bits when shifting to the right under the control of the lower bits of the shift code, while the output 25 of the switch 8 receives the output from 22s of the element 48 EXCLUSIVE OR 4 groups, if the cyclic shift is performed, the level of logical zero from input 28 - if a logical shift is performed and the value from the output 27 of an element AND 10 - if an arithmetic shift is performed

For the rightmost byte, the second switch 9 generates a parity of the sliding bits when performing a left shift under the control of the lower bits of the shift code, while the output 26 of the switch .9 receives the value from the output 22t of the group EXCLUSIVE OR 4i group, if a cyclic shift is performed, or logical zero level from the input

28 - if a logical or arithmetic shift is performed.

In the case of using only the right-hand shift in the device (the left-right cyclic shift is replaced in this case by the right shift by an additional shift amount code), the need to introduce the switch 9 is no longer necessary. In this case, at the first entrance

The switch 0 must be continuously fed into the logical zero level from the input 28 of the device.

Element AND 10 is designed to form a parity signal of sliding units when performing an arithmetic shift to the right. This signal is equal to one only when the device performs an arithmetic shift to the right by an odd number of negative digits.

0 numbers.

The device works as follows.

The operation of the device is considered in various modes on the example of a shift in

5 it is eight bytes of input information .. 364 by 19 bits (direct input binary code of the shift value 010011 is fed to the device 15 input).

Let the first byte of aiaaas.-.ae be

0 is the oldest and is accompanied by a check digit of the parity of K1, and the eighth byte ab7a-G) 9 ..Ag4 is the youngest and is accompanied by the check bit of the parity of K8.

5 Shift right logical. The control input of the generator 1 of the mask code receives the level of the logical unit from the input 14 of the device shift direction, which corresponds to the performance of the right shift. and the information inputs of the imaging unit 1 are supplied with the value of the lower three bits 152 of the input 15 of the device shift code (in this example, 011). In accordance with the work of shaper 1

5 (Table 1) at its output 17, in this case, a mask code 000001110 is formed, which then goes to the first inputs of blocks 2i-2a of elements AND groups, the second inputs of which are supplied with the values of the corresponding bytes 111-11e of the input information from input 11 of the device , and on the third inputs there are control bits 12i-12e corresponding to their own bytes from the input 12 of the control bits of the device. For the considered

5 cases at entrances 18i. 19i and 20i of block 2i of the group, the result of masking is formed as a combination of values 0000, О aatae and 0, respectively, at outputs 18a, 192 and 202 of block 22 - 0000, 0 a aa aie and O, respectively, and so on, at outputs 18i,

19c and 20e of block 2c - the result of masking as a set of values 0000, О

862363364 and 0.

Further, on the blocks of the elements of the OR group and the elements EXCLUSIVE OR 4i-4e of the first group, the parities of the bits put forward in each byte are formed. So, at the output 22i of the element 4i of the group, the parity of the PI vy OFO 0 (aOFO) is formed, at the output 222 of the element 42 - P2 vy OTO @ 000®0® -14 @ a15Fa1b 0, and so on, at the output 22v of the element 4c-Pv you О®О®00

О® OFE62F 363F 364 © 0.

Switch 8 generates the parity of bits inserted into the high byte (when performing a logical shift to the right, the parity of the sliding bits is zero), connecting the device level 28 logic input 28 to output 25 under control of signals from the device shift type 13.

Since the shift to the right is performed, the control inputs of the 6i-6th switch of the group receive the level of the logical unit, under the action of which the outputs of the 232-23a of the switch 62-63 of the group receive the parity of the nominated bits from the outputs 22i-22, respectively (the output of The 23i of the switch 6i of the group receives the parity value of the bits inserted into the high byte from the output 25 of the switch 8).

Thus, the inputs of the EXCLUSIVE or 5i-5e elements of the group receive three components: test bits 12i-12s of the corresponding bytes from the input 12 of the device control bits: the parity of the bits of the 4i-4a group from the outputs 22i-22a respectively; the parity of the bits to be pulled out from the adjacent left bytes from the outputs 23i-23s of switches 6i-6s of the group, respectively, which are the parity of the bits shifted into the corresponding bytes, At the outputs of elements 5i-5s of the group, predicted values of the check bits of bytes are formed when performing a shift under the control of the lower bits of the shift code. Thus, at the output 241 of the element 5i of the group, a check bit Kin Ki © Pi vyd® O is formed, at the output 242 of the element K2FR2 vyd @ P1 vyd and so on, at the output 24c of the element 5c - a check bit Ken KsOPs vyd.

In block 7, the shift of the control bits under the action of the control signals from the input 13 of the device shift type, the level of the logical unit from the input 14 of the device shift direction, and also under the control of

the higher bits 15i of the input 15 of the device shift code (in this example, the value of the three higher bits is 010), the control bits shifted at the outputs 24i-24e and received at the corresponding information in the moves of block 7 in accordance with its operation (Table 3). At the outputs of block 7 in this example, the following control bits are formed: 0.0, Kin, K2n. Ksp, "4n, Ksn, Kep. These check bits, which arrive at the output of the 16 check bits of the device, are the predicted parities of the result of the shifter.

The mismatch of at least one byte of the result of the shift of the values of its actual and predicted parity indicates the presence of either an error in the input information of the shifter or a malfunction in its equipment.

Arithmetic Right Shift In this mode, the device works similarly to the previous one. The only difference is that switch 8, forming parity of bits shifted into the high byte, connects output 27 of element 10 to control of signals from input 13 of device shift type to switch output 25. At the same time, at the output 27 of the element 10, a sign P is formed, which takes into account the parity of the shifted units when the negative number is shifted (in the considered example, the sign is executed because the right shift is performed and the level of the logical unit goes to the first input of the element 10 and the low-order 15z input 15 the shift code of the device connected to the second input of the element And 10 is set to one)

In accordance with the specified at output 24 of element 5 EXCLUSIVE OR groups, the check bit Kin Ki®P vyfp is formed.

The right shift is cyclical. In this mode, the device operates similarly to the described mode. The difference is that the switch 8, forming parity pushed into the high byte of the bit, connects the output 22 of the EXCLUSIVE OR 4a element of the group under control of the signals from input 13 of the device shift type to the output 25 of the switch 8, since bits shifted into the high byte when performing the cyclic right shift under the control of the lower bits of the shift code. In accordance with the specified at the output 24i of the EXCLUSIVE OR 5i element of the group, a check bit is generated,

In addition, in block 7, the shift of the control bits under the control signals,

coming from the input 13 of the device shift type, the logical unit level of the device shift direction coming from the input 14, as well as under the control of the higher bits 15 of the input 15 of the shift code of the device (in the considered example, the value of the three higher bits equals 010) control bits generated at the outputs 24i-24e and received at the corresponding information inputs of block 7 in accordance with its work (Table 3)

In this example, at the outputs of block 7, the following check bits are formed: K p Kin Cap Ccn 4P Ksn, Ken These check bits, which are the predicted offset results, arrive at the output of 16 check bits of the device

Shift left logical To the control input of the mask code generator 1, the logical zero level is received from the device shift direction input 14 corresponding to the left shift, and the data inputs of the Shaper 1 are supplied with the value of the lower three bits 152 of the device shift code input 15 (in the considered example 011) In accordance with the operation of shaper 1 (Table 1), in this case, the mask code 1110 UOCO 0 is formed at its output 17, which deaeg pecks on the first inputs of blocks 2i 2g m whose inputs are fed to the corresponding x bytes 11i-11h of input information from input 11 of the device and the third control i2i- 12s descents of the corresponding bytes e input 12 control bits of the device For the considered incident or output 18i 19i and 20i of block 2i, the result of masking is formed as a set of values aia23T 0 0000 and 0 and t d, at outputs 18p 19a and 20s - the result of masking in the form of a set of values of a tagz 0 to 0 0000 and O

Next, on blocks 3i-3s of the elements of the OR group and the elements of the EXCLUSIVE OR of the first group, the parities of the nest n each byte bits are formed

Thus, at the output 22i of the element 4i of the group, a parity of Pout aW 32 az O® cha vyhog.o 2; elemental Rdpdout, yue a: SOSOj Of v t h HJ output 22z of element 4f forms the RTPT Ravid-ao © sv $ No., & 000 and Oc 0 © 0.

The switch 9 forms a check (pjj series, divided into the lower byte (when performing a logical and arithmetic shift in the parity of the retractable bits to the left, zero), bus 28 devices

to output 26 controlled by signals from input 13 of the device shift type

Since the shift to the left is performed, the control inputs of the switches of the group receive a logic zero level, under the action of which the outputs 231-23 of the switches 6i-6 of the group receive the parity values of the advancing bits from the outputs 222-228, respectively, and output 23c of the switch 6a the group receives the parity value of the bits inserted into the low byte from the output 26 of the switch 9.

Thus, the inputs of the EXCLUSIVE or 5i-5a elements of the group receive three components: test bits 12i-12a of the corresponding bytes from the input 12 of the device, the parity of the bits from the outputs of the outputs 22i-22a, respectively, and the parity of the advancing bits of the neighboring right bytes from the outputs, respectively. At the outputs of elements 5i-5e of the group, the predicted values of the check bits of the bytes are formed when performing the shift under the control of the lower digits of the shift code. Thus, at the output 24t of the element 5i of the group, a control is formed first discharge Kin-Kut7 Rtvyd fR2vyd outlet 24g K2 element Q © R2VYD R2VYD ETC, the output member 5a 24fi K (n-Ap © RavydfO

In block 7, the shift of control bits under the action of signals coming from the input 13 of the device shift type is the logical zero of the device shift direction coming from the input 14, as well as under the control of the higher bits of the device shift code 15i 15i (in this example, the value of the higher bits 010) left-shift of the logical control bits generated at the outputs 24i 24s and received at the corresponding information inputs of block 7, in accordance with its work (Table 3) In this example, you In block 7 moves, the following check bits Ksn Ksn, KG, Kyn, Kan О О are formed. These check bits, which are predicted by the parity of the sdpigatel result, arrive at the output of 16 control bits of the device.

Arithmetic left shift In this mode, the device works in the same way as in the previous mode and for the same data the same values of the predicted parities of the shift result are formed.

Left Shift Cyclic In this mode, the device operates in the same way as the left shift mode.

The difference is that the switch 9, forming the parity of the bits inserted into the low byte, connects the output 22 of the EXCLUSIVE OR 4i element of the group under control of the signals from input 13 of the device shift type to the output 26 of the switch 9, since bits shifted into the lower byte when performing a left-shift cyclical under the low-order code bits of the shift code. In accordance with the specified at the output 24c of the EXCLUSIVE OR 5th element of the group, a control bit Ravid & Rshyd.

In addition, in block 7, the shift of control bits under the control of signals coming from the input 13 of the device shift type, logic level zero coming from the device 14 control shift of the device, as well as under the control of the higher bits 15 of the input 15 of the device shift code (in the In the example, the value of the three most significant bits is 010) the left-shift test bits generated at the outputs 24i-24a and received at the corresponding information inputs of block 7 are shifted in accordance with its operation (Table 3). In the considered example, the following control bits are formed at the outputs of block 7: Кзп, K4n, Ksn, Кбп,, Kan, Kin, К2П. These check bits, which are the predicted parity of the shift result, arrive at the output of 16 check bits of the device,

The device has autonomous (independent) parity (or oddness) control, which does not require the introduction of additional links to the shifter and does not limit the options for its implementation, while it is possible to predict parity for each group of bits of the shift result, accompanied by its own check bit.

Claims (1)

An apparatus for predicting the parity of a shifter result, comprising a mask code generator, a group of element blocks. AND, two groups of EXCLUSIVE OR elements, a group of switches, a check digit shift block, two switches and an AND element, connected to the input of the device direction setting shift, the lower limit of the input of the device shift code setting and the high bit of the information input of the device, the output of the mask code generator is connected to the first inputs blocks of elements AND groups whose input specifies the direction of the shift of the device is connected to the control input of the mask code generator, the control inputs of the group switches and the input of the shift direction of the control bits shift block whose input of the shift type is connected to the control inputs of the first and second switches and is the input of the device shift type setting, the information input of the code generator the mask is connected to the lower bits of the input entry of the device shift code, the input of the shift block offset value of the control bits is connected to the higher bits of the input of the device shift code entry, the second inputs of the blocks of elements AND groups are connected to the corresponding groups of bits of the information input of the device, output 1 th element is EXCLUSIVE OR first group connected to the first input of the 1st element EXCLUSIVE OR of the second group, the second and third inputs of which are connected to the output of the 1st switch of the group and the i-th bit of the input of the control bits of the device, respectively (1 im, where m is the number of elements EXCLUSIVE OR first group), the outputs of the EXCLUSIVE OR elements of the second group are connected to the corresponding information inputs the control bits shift block, the outputs of which are connected to the corresponding bits of the output of the control bits of the device, the output of the first switch is connected to the first information input of the first switch of the group, the output of the j-ro element EXCLUSIVE OR of the first group is connected to the first information input (j + 1) - switch group (1 j m-1), the output of the k-th element EXCLUSIVE OR of the first group is connected to the second information input (k-1) -ro of the switch group (2 k m), the output of the second switch is connected to the second information input of the last the switch of the group, the outputs of the first and last elements EXCLUSIVE OR of the first group are connected to the first information inputs of the second and first switches, respectively, the output of the AND element is connected to the second information input of the first switch, the third input of the first switch and the second input of the second switch, This is because, in order to reduce the hardware cost of the device, it contains a group of blocks of OR elements, with the first and second outputs of each block Single elements and the group are respectively connected to first and second inputs of the corresponding block element or group. the output of which is connected to the first input of the corresponding element EXCLUSIVE OR of the first group, the second input of which connected to the third output of the corresponding block of AND elements of the group, the third input of the 1st block of elements AND of the group is connected to the 1st bit of the group of control inputs of the device. Note. R, K - direct and inverse levels of the logic signal, which is potential at the control input of the driver 1 (at the moving device shift direction). Table 1 Note. Hf - information at the i-th information input of Spock 7; P-0 when forming parity check bits; P 1 in the formation of test bits for oddness. . . st I