SU1300477A1 - Shifting device with checking - Google Patents

Abstract

The invention relates to computing and is intended for the organization of a shift in high-performance information processing systems, the control of which is carried out by parity 2j. The aim of the invention is to enhance the functionality by performing arithmetic and cyclic shift with control. The goal is achieved in that the device containing the shift unit 1, the decoders 2, 3 zero, the additional code generation unit 5, the co1 mutators 6-8, the elements EXCLUSIVE OR 9-12, 20, the block 16 elements AND, the block 18 elements EXCLUSIVE BL, element 19, the reverse code generation unit 4, adder 13, mask drivers 14, 15 of the mask code, AND block 17, and a shift type decoder 21 with corresponding links are entered. 1 hp f-ly, 2 ip., 1 tab. U 2St (L of about 4 33 Fi. 1

Description

one

one

The invention relates to computing and can be applied in high-performance information processing systems, the control of which is organized by parity.

The aim of the invention is to enhance the functionality by performing arithmetic and cyclic shift with control.

Figure 1 shows the block diagram of the device for the shift with the control; Fig. 2 is a functional diagram of the formation of a mask code (for the case of processing in the device eight bytes of information, each of which has its own check bit).

The device for shifting with the control (FIG. 1) contains the shift unit 1, the first decoder 2 zero, the second decoder 3 zero, the reverse code generation unit 4, the additional code generation unit 5, the first commutator 6, the second switch 7, the third Hommutator 8, elements 9-12 EXCLUSIVE OR from the first to the fourth, respectively, adder 13, the first driver of the 14. mask code, the second driver of the mask code 15, the first block 16 of the elements And, the second block 17

AND elements, block 18 elements EXCEPT-ZO code.shift, if the device is NEXT OR, element AND 19, five elements EXCLUSIVE OR 20, decoder 21 types of shift, input 22 of the device shift code, high order 22 input 22, lower bits 22g of input 22, lower bit 22. input 22, device shift direction input 23, device shift type input 24, device check bits 25, decoder outputs 26-29, device check bits output 30, error output 31 device, device data input 32, high-resolution 32 input 32, output 33 of the result device a.

Shaper 14 (15) of the mask code (FIG. 2) contains multiplexers 34-39, first and second control inputs 40 and 41 of the shaper, information input 42 of the shaper, output 43 of the shaper, multiplexer 44.

The functional purpose and implementation of the basic units and units of the device for shifting with control, for certainty, assumes that the device processes eight bytes of information, each of which is; has its own parity check.

1300477

The shift unit 1 is designed to perform, under the action of the corresponding control signals, logical, arithmetic and cyclic information shifts.

The first decoder 2 zero is designed to generate at its output a potential of logical 1, when the three most significant digits of the shift code are zero and the information shift signal to the left is present at the input 23 of the device shift direction. The second decoder 3 zero is also designed to generate a logical 1 at its output, however, when the three lower digits of the shift code are zero and the device shifts information to the left.

The Node 4 unit automatically regulates the return code from the value of the three higher bits of the shift code, and in node 5, the additional code from the value of the three lower digits of the shift code (it is assumed that a forward code is always fed to the input 22 of the shift code of the device, regardless of the direction of the shift shift values).

 The first switch 6 passes to the output the value of the three lower bits.

five

0

The information shifts to the right. Otherwise, an additional code of the value of the three lower bits of the shift code, formed in the node 5 of the formation of the additional code, is transmitted to its output. The second switch 7 passes to the output the value of the three higher bits of the shift code when the device shifts the information to the right. Otherwise, the opposite code transmits the code of the value of the three higher bits of the shift code, obtained in the node 4 form1) of the reverse code. The third switch 8 performs a sampling from the input of that byte of input information, the bits of which can be partially extended in the process of shifting information in the device. This byte is sampled according to the following rule.

Let the most significant byte of the input information of a device be the first, the sequence number, and the lowest one, the 5th, the eighth serial number. Then, when a code 000 arrives at the control input of the switch 8, its output is the eighth (lowest) byte of the input information, with the code

five

0

information, the bits of which are either not generally put forward during the transfer of information in the device, or partially put forward.

001 - the seventh, with code 010 - the sixth, etc., with code 111 - the first (most significant) byte of input information.

The first driver 14 of the mask code 5, together with the first block 16 of the elements And, is intended to select the end of the first driver 14; the bits of those bytes of the input mask code.

Table 1 describes in detail the functions

information, the bits of which are either not put forward at all during the process of shifting information in the device, or are partially put forward.

Creation of the first shaper 14a masks.

Table 1 describes in detail the functions of Table 1.

51

The second driver 15 of the mask code together with the second block 17 of the elements And allocates three bits of the byte selected by the third switch 8, which must be pushed in the process of shifting the information in the device. The second driver 15 of the mask code can be implemented in the same way as the former driver of the mask code 14,

Block 18 includes eight EXCLUSIVE OR elements, the outputs of which form check bits (parity) for eight bytes of information obtained at the output of shift block 1.

Element I 19 is intended for forming a signal that allows parity of the retractable units when the arithmetic shift to the right is performed in the device. This signal is equal to one only when an arithmetic right shift is performed in the device by an odd number of bits of a negative number.

- The element EXCLUSIVE OR 9 performs the modulo summation of the two following groups of addends :; check bits of those bytes of input information, the bits of which are

The operation of the device is considered a forward binary value code.

in various modes on the example of shift shift 110101). it has eight bytes of input information. Let the first byte be aa aa,.,., atsii, jaj, .... , and on 53 binary .. - i i s

bit (the input 22 of the auxiliary information device is the oldest and is accompanied by a control

O

five

five

they are not inserted in the process of shifting information in the device or are already partially loaded (these control bits come from the output of the first block of 16 I elements); the shifting bits of that byte of input information, the discharge of which is only partially lost in the process of shifting information into

-ABOUT

device (these bits come from the output of the second block 17 of the elements I); check bits of all bytes of the device output information; coming from the output of block 18; a signal that takes into account the parity of the units being moved during the arithmetic shift to the right of a negative number (the value of this signal is supplied from the output of the And 19 element).

In fact, on the element EXCLUSIVE OR 9, the values of the predicted and directly formed parities of the result are compared. A single signal at the output of the EXCLUSIVE OR 9 element is an indication of an error.

The decoder 21 of the type of shift is performed; the control signals are generated depending on the type and direction of the shift and is described in Table 2.

0

table 2

shear 110101). Let the first byte aa a,.,., And .. - i i з

eight

input information is the oldest and is accompanied by a control

the discharge of K, and the eighth byte aa a, a, a, a, a-, is the youngest OS

and it is accompanied by a check bit Kg.

The right shift is logical. The inputs 23 and 24 of the direction and type of shift of the device receive signals that set up the shift block 1 to perform the logical shift of information in it to the right. At the same time, a code 10 is formed at the first and second outputs 26 and, 27 of the decoder 21, and a zero potential at its third control output 28. As a result, the first shaper 14 of the mask code is controlled by code 10 and the second shaper 15 of the mask code by code 01. Since the device shifts the information to the right, then the information input of the first shaper 14 of the mask code and the control input of the third switch 8 off the output of the second switch 7 is supplied with the value of the direct code of the three most significant bits of the shift code (for the considered example 110), and the value of the direct code of the three lower bits of the code c arrives at the information input of the second generator 15 of the mask code engine (for the considered example 101). The third switch 8 selects from the output 32 of the device data the second byte 9 "" "), the input information, the output of the first driver 14 generates a mask code 11000000, and the output of the second generator 15 - mask code 00011111 (see Table 1). Using the masking codes formed in the device, the output of the first block of 16 elements And is obtained the value of K K-Oooooo, and the output of the second block of 17 elements I - the value of the LLC a and a a. These values, summing modulo two on element 9, form the value of the predicted parity of the result P

TO

17 1 H

which

© a, ® a ,,, is compared with the value of the actual parity of the result obtained at the output 33 of the device.

Arithmetic right shift.

In this mode, the device works like the previous one. The only difference is that the potential of logical 1 is formed at the output 28 of the decoder 21, and the shift unit 1 through the shift type input 24 is tuned to perform arithmetic information shift in it. For the same data, in this case, the following value of the predicted parity P K, + Kj® a, @ а a ® (J) a + P is formed, where P is a sign that takes into account the parity of the inserted particles when the negative number is shifted (the value of the sign formed at the output of the element 19).

Shift left logical.

The inputs 23 and 24 of the direction and type of the device shift receive signals that set up the shift unit 1 to perform the logical information shift to the left in it. At the same time, code 01 is generated at outputs 26 and 27 of the decoder 21, and zero potential is output at its output 28. As a result, the first shaper 14 of the mask code is controlled by code 01, and the second shaper 15 of the mask-code code 10. As the device shifts the information left, the value of the mask code from the output of the adder 13 is applied to the information input of the first shaper 14 of the mask code the additional code of the three higher bits of the shift code (for the considered example 010), the information input of the second generator 15 of the mask code from the output of node 5 through the first switch 6 also receives the value of the additional code, however three lower times the shift code rows (for the considered example 011), and the return input of the three higher bits of the shift code (for the considered example 001) is fed to the control input of the third switch 8 from the output of node 4 via the second switch 7. The third switch 8 selects from the input 32 of the device data the seventh byte aa a, a,, ..., a,

4E so 51 S6

INPUT information, the mask code 00000011 is generated at the output of the first generator 14, and the mask code 11111000 is output at the output of the second generator 15 (see Table 1). Using the masking codes formed in the device, the output of the first block of 16 elements And is obtained the value of OOOOOOK Kg, and the output of the second block of 17 elements I is the value of a and 000. These values, summed together on element 9 modulo two, form the value of the predicted parity of the result P K, ® K, ® a, d® a ,, ® a., ® a ,,,

which is compared with the value of the actual parity of the result obtained at the output 33 of the device.

When the information is shifted to the left, if the three higher j or three lower bits of the shift code (or both simultaneously) are equal to zero, single signals are generated at the outputs of the corresponding decoders 2 and 3 zero, which invert the values of the signals at the control inputs of the drivers 14 and 15 mask codes.

Shift, left arithmetic.

In this mode, the device operates f5 in the same way as in the previous mode, and for the same data the same value of the predicted parity is formed.

Cyclic shift.20

It is assumed that in the device this shift is performed only to the right (shifting left and right cyclically does not make sense). At entrances 23 and 24 do not restrict the implementation options.

Claims (2)

1. A device for shifting with a control, containing a shift unit, three switches, an additional code generation unit, the first block of AND elements, the AND element, the block of EXCLUSIVE OR elements, five elements EXCEL SINGER OR, and two zero decoder, and the device data input is connected to the information input of the shift block, the inputs of the shift value and the shift direction of which are connected to the inputs of the shift code and the direction of the shift of the device, respectively, the output of the shift block is connected to the input of the block of the EXCLUSIVE OR elements and is the output p According to the result of the device, the output of the node for the formation of an additional code is connected to the first terminal,. the formation input of the first commutator and the type of shift of the device, along the control input-25, of which are connected the signals that set up the block dinene with the input of the device shift direction and with the control input of the second switch, the second information input of the first switch is connected to the first input of the first element EXCLUSIVE 1 shift to perform in it a cyclic shift to the right and blocking the operation of the second block 17 of the elements I. The latter are effectively excluded from the operation of the device the second generator 15 of the mask code and the third switch 8. At the same time, at outputs 26 and 27 of the decoder 21, dinene with the input of the device shift direction and with the control input of the second switch, the second information input of the first switch is connected to the first input of the first element EXCLUSIVE ., „„ „OR, characterized by The 11% code at output 28 is null-35 extensions of functionality due to performing arithmetic and cyclic shift with the control €; m, it contains the second block of AND elements, an adder, two for-. howl a signal, as a result of which, at the output of the first generator 14 of the mask code, regardless of the value of the code, a code consisting of only 11111111 units is formed at its information input (see Table 1). At the output of the first block of 16 elements, And the value K, K, K is obtained. K., Kg, which the worldviewer of the mask code, the reverse code formation node and the shift type decoder, the output of the reverse code formation node being connected to In other words, summing modulo two on the element by the information input of the second ment 9, forms the value predicted, a- 45 p, the information bath of the parity of the result P - +. Kg. This value is compared with the value of the actual parity of the result, 50 the input of which is connected to the input of the reverse code generation node, with the information input of the first decoder zero and with the higher bits of the input of the device shift code, the lower bits of the input of the shift code are connected to the input of the additional code generation node from the device on the device code 33. An additional positive effect from the use of the invention is the reduction of the monitoring equipment and the expansion of the area by the application input of the second decryption of the device due to the organization of the zero torus, the input of the shear direction in it is independent control of the even device connected to the difference inputs solutions of the first and second deciphering links with the shift unit and the level zero and with the transfer input summan limited implementation options. Invention Formula 1. A device for shifting with a control, containing a shift unit, three switches, an additional code generation unit, the first block of AND elements, the AND element, an EXCLUSIVE OR block of elements, five EXCLUSIVE OR elements, and two zero decoder, and the device data input is connected to the information the input of the shift block, the inputs of the shift value and the shift direction of which are connected to the inputs of the shift code and the shift direction of the device, respectively, the output of the shift block is connected to the input of the block of the EXCLUSIVE OR elements and is the output p On the result of the device, the output of the node for the formation of an additional code is connected to the first in which control input is connected dinene with the input of the device shift direction and with the control input of the second switch, the second information input of the first switch is connected to the first input of the first element EXCLUSIVE capabilities due to the implementation of arithmetic and cyclic shift with control €; m, it contains the second block of elements And, adder, two for-. the worldviewer of the mask code, the reverse code formation node and the shift type decoder, the output of the reverse code formation node being connected to  information input of the second p information  information input of the second p information the input of which is connected to the input of the reciprocating code formation jia, with the information input of the first decoder zero and with the higher bits of the input of the device shift code, the lower bits of the input of the shift code of which are connected to the input of the node of the additional code formation, with the information input of the second decoder zero, the shift direction input of the device is connected to the resolution inputs of the first and second decoders zero and to the transfer input of the adder, the input of which is connected to the output of the second switchboard and t controlling the input of the third switch, whose information input is connected to the data input of the device, the outputs of the adder and the first switch are connected to the information inputs of the first and second drivers of the mask code, respectively, the outputs of which are connected to the first inputs of the first and second blocks of elements And, respectively, the second inputs of which are connected with the input of the control bits of the device and with the output of the third switch, respectively Actually, the outputs of the second block of elements AND, the block of elements EXCLUSIVE OR, and the element AND are connected respectively to the second, third and fourth inputs of the first element EXCLUSIVE OR, whose output is the output of the device error, the output of the block of elements EXCLUSIVE OR is the output of the control bits The 20th and second control inputs of the mask code generator, the first information inputs of the first, second and third multiplexers, the second information inputs of the second, three-way, shift-type and forward-25 and fourth multiplexers, the device shift section are connected to the third information inputs of the third, respectively with the inputs of the bits of the decoder type of shift, the outputs of which are connected respectively to the fourth and fifth multiplexers, the fourth information inputs of the fourth, fifth and sixth multiv The second and third plexer inputs are connected to the output of the EXCLUSIVE OR seedlings, to the first input of the AND element and to the third input of the second block of AND elements, the shift type shift input is connected to the device shift type input, the second input of the AND element is lower-order the house of the input of the device shift code, the third input of the element I is connected to the highest input of the data of the device, the first inputs of the second and third elements EXCLUSIVE SCHSCH are connected respectively to the first inputs of the fourth and fifth elements of the EXCLUSIVE CEE OR, the output of the first decoder zero is connected to the second inputs of the second and third elements EXCLUSIVE OR, the outputs of which are connected to the first and second controls of the first shaper code masks, respectively, the output of the second and sixth multiplexers are connected to th decoder zero is connected to wto, o The primary inputs of the fifth and fourth elements are EXCLUSIVE OR, the outputs of which are connected to the first and second control inputs of the second generator of the mask code, respectively. 2. The device as claimed in claim 1, wherein the mask code generator contains seven multiplexers, the second and third bits of the information input of the mask code generator are connected to the first and second control inputs of the multiplexers one through six, respectively the first bit of the informational input of the mask code generator is connected to the control input of the seventh multiplexer, the first and second information inputs of which are connected respectively to the first and second control inputs of the mask code generator First data inputs of the first, second and third multiplexers, second inputs of the second information, tre5 tego and fourth multiplexers, the third informational inputs of the third, the third and fourth multiplexers, the third information inputs of the third, the fourth and fifth multiplexers, the fourth information inputs of the fourth, fifth and sixth multiplexers, the second, third and fourth information inputs of the first multiplexer, the third and fourth information inputs of the second multiplexer, the fourth information input of the third multiplexer is connected to the first information input of the seventh multiplexer, the second information input of which is connected to the first information input of the fourth multiplexer, with the first and second information inputs of p that multiplexer, with the first, second and third informational inputs of the sixth multiplexer, the second information input of the seventh multiplexer, the outputs of the first, second and third multiplexers, the outputs of the seventh, fourth, fifth the output of the mask code driver. five 13. Editor L.Povkhan Compiled by A. Klyuev Tehred A. Kravchuk : Order 1150/48 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader L. Patay