SU1550582A1 - Storage - Google Patents

Abstract

The invention relates to digital computing and can be used in computing systems. The aim of the invention is to expand the field of application of the device due to the possibility of indirect addressing. The memory device contains a write signal shaper 1, a drive 3, a decoder 4, an address shaper 5. The introduction of the address mode shaper 6 allows the indirect addressing method to be implemented. 2 Il.

Description

FIG. one

. 3

The storage device (memory) refers to digital computing and can be used in computing systems,

The aim of the invention is to expand the field of application of the device due to the possibility of indirect addressing.

FIG. 1 shows a diagram of a storage device; in fig. 2 is a block diagram of an addressing mode shaper.

The memory (Fig. 1) contains a shaper 1 of the recording signals, information inputs 2, a storage device 3, a decoder 4, a shaper 5 of address signals, a shaper 6 of the addressing mode, address inputs 7, information outputs 8, an input 9 of the addressing mode type.

The addressing mode driver (Fig. 2) contains a switch 10, second information inputs 11, address output 12, control input 13, multiplexer 14, first information inputs 15, information outputs 16.

The memory works as follows.

In the information recording mode, the signals of the address code A ,, ,, .., А come from inputs 7 to the driver 6. The control signal received at the input 9 of the addressing mode driver allows the address code to pass from external inputs 7 to the driver 5 of the address signals. The shaper 5 in the necessary way converts the signals of the address code (coordinates the external and internal logic levels, amplifies the signals, forms an additional address code A ,, ..., A) and transmits it to the decoder 4. The tracker, in accordance with the received address code, chooses in drive matrix 3 memory elements (ES) to which information will later be recorded (or read in the information reading mode). The shaper 1 of the recording signals converts the information signals D / I Dp arriving at it from the input 2 of the charger (coordinates the external and internal logic levels, amplifies them, generates an additional code DJ, ..., DpO and ensures the recording of the input information in accordance with the address code in Selected ES Drive 3.

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In the information reading mode, with the direct addressing mode, the EF sample in drive 3 is performed in the same way as in write mode: the address code signals from inputs 7 of the memory through the driver 6 are fed to the driver 5 and further through the decoder 4 to the drive 3. Read from The storage device 3, under the influence of the control signal at input 9, is fed through the imaging unit 6 to the output 8 of the memory.

In an indirect addressing method, the output of the previous operation is used to perform the next operation. For this, a control signal at input 9 prohibits the passage of an address code from inputs 7 to shaper 5 and allows the output information used as an address code to pass from accumulator 3 to shaper 5 of address signals.

The ability of the memory device to be used with direct and indirect addressing is provided by the addressing mode generator 6 (Fig. 2). Depending on the control signal at input 13, multiplexer 14 transmits information from inputs 15 to information outputs 16 (with the direct addressing mode) or to the second input group of switch 10 (with indirect addressing methods). The switch 10, in turn, under the action of the same control signal at input 13 connects to address outputs 12 either inputs 11 (with direct addressing mode) or the second group of outputs of multiplexer 14 (with indirect addressing mode).

Thus, the introduction of the addressing mode shaper into the memory allows one to implement an indirect addressing method, which greatly expands the scope of the memory application, especially when used in computer systems in conjunction with microprocessors.

Claims (1)

Invention Formula A memory device containing a recording signal driver, whose inputs are the information inputs of the device, an address signal generator, a decoder and a drive, whose information inputs are connected to the outputs of the FIRMI 51 the write signal solver, the outputs of the address signal generator are connected to the inputs of the decoder, the outputs of which are connected to the accumulator address inputs, in order to expand the application area by providing indirect addressing, the address mode generator is inserted into the device, and the first information inputs are connected to the information outputs of the storage device, the second in 05826 the formation inputs of the addressing mode generator are the device’s address inputs, the address signal generator inputs are connected to The address outputs of the addressing mode generator, whose information outputs are informational outputs of the device, the control 10 input of the addressing mode generator is an input for setting the addressing mode of the device. //; j g 12 / ten one /four 15 ± J Y, 2