SU1531199A1 - Frequency comparator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in radio devices designed to control the frequency of signals. The purpose of the invention is to increase the speed with a given noise immunity. In the device containing the pulse counters 6.7 and one-shot 3, entered the triggers 1 and 9, the pulse shaper 5, the elements OR NOT 2,4 and switches 8,10. The threshold is set by the duration of one-shot pulses 3. The output of the element OR-NOT 2 passes pulses if the frequency is less than the threshold, and the output of the element OR-NOT 4 - if the frequency is greater than the threshold. To switch the trigger 9, it is necessary that the number of pulses with a frequency greater (lower) than the threshold, equal to the conversion factor of the counter 7 (6), is also passed. 2 Il.

Description

SP

with

with so

315

The invention relates to a pulse technique and can be used in radio devices designed to control the frequency of signals.

The aim of the invention is to improve the speed at a given noise immunity of the frequency comparator.

FIG. 1 shows the structural cx of the frequency comparator; figure 2 - timing charts of the device

The frequency comparator contains a counting trigger 1, the direct output of which is connected to the first input of the first element OR NOT 2 and the start input of the one oscillator 3. The inverse output of the counting trigger 1 is connected to the first input of the second element OR NOT HE and the one-vibrator reset input 3. The output of the one-shot 3 is connected to the input of the imaging unit 5 pulses, the output of which is connected to the second inputs of the first and second elements OR NOT 2 and D. The output of the first element OR NOT 2 is connected to the reset input of the first counter 6 pulses and the counting input of the second counter 7 pulses. The output of the second element ILM-NOT 4 is connected to the counting input of the first counter 6 and the reset input of the second counter. One of the outputs of the first counter 6 using the switch 8 is connected to the S-input of the RS flip-flop 9 and one of the outputs of the second counter 7 using the switch 10 is connected to the R-input of the RS-flip-flop 9, the output of which is connected to the output bus 11. The input bus 12 is connected to the input of the counting trigger 1.

The function of the pulse driver 8 performs a differential circuit consisting of a capacitor and a resistor.

Frequency comparator works as follows.

A sequence of rectangular pulses U (Fig. 2a) with varying frequency is fed to the input of counting flip-flop 1, designed to eliminate the influence of the duty ratio of the input pulses on the operation of the frequency comparator. For each negative front of Ud pulses (FIG. 26), coming from the direct output of the counting trigger 1, a one-shot 3 starts. If the frequency of the input fex pulses is less than the threshold frequency of the frequency comparator (Fig. 2, the time interval to, t, t,, t ..., tj)

1994

then the one-shot 3 generates positive pulses 1C duration

C1

With op

(Fig. 2d) If fg, f

pore

(Fig. 2, time interval t, ... to), then the one-shot 3 is forcedly reset by negative edges of the U- pulses (figure 2c) coming from the inverse output of trigger 1, and the one-shot 3 forms pulses and, for a duration D

one

-.For5 0 5 o

with

five

0

0

The globalizer 5 on the negative fronts of the No. 1 pulses b i forms short pulses U5 (Fig. 2e). With fgx fnop, the impulses u5 will pass to the output of the element OR-NOT 2, and for then the output of the element 1-SHI-NOT i. The pulses Ug, from the output of the element OR NOT 2, are fed to the counting input of the second counter 7 and the reset input of the first counter 6, and the pulses UT- from the output of the element OR NOT are fed to the reset input of the second counter 7 and the counting input of the first counter 6. From the output of the first counter 6 using the switch 8, the pulses Ug (Fig. 2h) are fed to the S input of the RS flip-flop 9, and from the output of the second counter 7 using the switch 10, the pulses Ug are fed to the R input of the RS flip-flop 9. High voltage L / dNa output RS-flip-flop 13 indicates that fg (Fig. 2k).

The first counter 6 is designed to increase the reliability of the output information when interference pulses appear in the input signal U in the case of fftn fnop. If the resulting frequency exceeds the fnop value, then pulses appear at the output of the element OR-HE 4. When these pulses are directly applied to the S input of the RS flip-flop 9, the latter will be set to a state that falsely signals that fn, f

 -Bx fnop

VC

nop When serving the same

of these pulses to the counting input of the primeval counter 6 and connecting the 5th input of the RS flip-flop 9 to the output of the first counter 6 with a recalculation factor n, the RS-flip-flop 9 triggers when n pulses arrive at the counting input of the first counter 6. If moment at the reset input of the binary counter 10 receives at least one pulse from the output of the element OR NOT 2, then the first counter is reset5153

6, and RS flip-flop 9 retains its state. To eliminate the influence of interference pulses on the operation of the frequency comparator, the conversion factor n must be greater than the maximum number of pulses generated at the output of the OR-NOT A element as a result of the interference pulses. Since the number of these pulses is random and cannot be accurately calculated, the conversion factor n is selected using switch 8. With fgx fnop, there are interference pulses at the input of the frequency comparator to the S input of RS flip-flop 9 sequentially, in order of increasing the conversion factor, the outputs of binary counter 10 are connected until a stable low voltage level is established at the output of the frequency comparator ire. In this case, the interference pulses will not lead to false triggering of the frequency comparator.

Similarly, with the help of the second counter 7, the frequency comparator is protected against the false triggering of one or several input pulses in the event that

f-f, fnop

The switching of the RS flip-flop 9 always occurs after a predetermined number of pulse periods arriving at the countable input of one of the counters 6 and 7, after this counter has been reset to zero for the last time. In from 996

known device this time interval had a random addition. Consequently, the speed of the proposed device is higher.

Claims (1)

Invention Formula A frequency comparator containing the first and second pulse counters and a one-shot, characterized in that, in order to provide an opportunity to increase speed with a given noise immunity, a counting trigger, an RS-trigger, a pulse shaper, and the first and second elements ШИИ-НЕ, the first and second switches, the input of the counting trigger is connected to the input width, the direct and inverse outputs to the one-shot start and reset inputs, as well as to the first inputs of the first and second IPI-NE elements, output one Ovibrator through pulse shaper connected to the second inputs of the first and second elements SHI-NOT, the outputs of which are connected to the reset inputs of the first and second pulse counters, respectively, as well as the counting inputs of the second and first pulse counters, respectively, the outputs of which are connected via the second and first switches, respectively with the reset inputs and install the RS-flip-flop, the output of which is connected to the output bus. Vl,. ". - “-J But -Vj -Kj 4  : 3 z r 5 5 5 “zkaso“ Oflcaftj rriS Compiled by A. Smirnov Editor G. Volkova Tehred M. Didyk Korrektor M. Kucher va Order 7965/55 Circulation 884 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and publishing plant Patent, Uzhgorod, st. Gagarin, 101 Subscription