SU1691947A1 - Phase-pulse converter - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automated process control systems, in the following phase-displacement transducers, etc. The purpose of the invention is to expand the dynamic range and increase the reliability of the conversion. The pulse-phase converter contains an analog switch 1, shapers 2, 3 pulses, IL-4 element, voltage source 5, comparators 6. 7, integrators 8, 9 with reset, counting trigger 10 and generator 11 clock pulses. Introduction of the additional elements OR 12, 13, triggers 14, 15, comparator 16, module allocation unit 17, phase fixation unit 18 at overloads, summing amplifier 19 with their connections allowed to expand the range of input convertible signals and the range of phase control output pulses, eliminate the disappearance of pulses during overloads, as well as improve noise immunity, thereby significantly increasing the reliability of the phase-pulse converter. 4 il.

Description

The invention relates to a pulsed technique and can be used in automated process control systems in the following phase-displacement transducers, etc.

The aim of the invention is to expand the dynamic range and increase the reliability of the conversion.

FIG. 1 shows a functional diagram of a phase-pulse converter; in fig. 2 is an example of a constructive implementation of a phase locking unit during overloads; in fig. 3 - time diagrams of the operation of a phase-pulse converter; in fig. 4 - timing diagrams of the phase locking unit during overloads.

Phase pulse converter contains analog switch 1, shapers 2, 3 pulses, element OR 4, source 5 of reference voltage, comparators 6.7, integrators 8, 9 with reset, counting trigger 10, generator 11 clock pulses, elements OR 12,13, RS-triggers 14,15, comparator 16, module allocation unit 17, phase fixing unit 18 in turn, summing amplifier 19, input in 20, zero potential bus 21 and output bus 22, while the output of summing amplifier 19 is connected to the first input of the analog switch 1, the second input of which It is connected to the output of the module 17 allocation module and the second input of summing amplifier 19, the first input of which is connected to the output of the source 5 of the reference voltage and the inputs of the integrators 8, 9 with a reset, the reset inputs of which are connected respectively to direct and inO

about

6

the upstream outputs of the counting trigger 10 and the second inputs of the elements OR 12, 13, respectively, the first inputs of which are connected to the generator output 11 clock pulses, the input of the counting trigger 10 and the second input of the phase fixing unit 18 in case of overloads, the output of which is connected to the output bus 22, and the first input - with the output of the element OR 4, the inputs of which are connected to the outputs of the formers of 2.3 pulses, the inputs of which are connected respectively to the inverting inputs of the RS flip-flops 14, 15, the inputs of the set to zero which are connected respectively to the outputs and the elements OR 12, 13, and the installation inputs to the unit, respectively, with the outputs of Comparators 6, 7, the non-inverting inputs of which are connected respectively to the outputs of the integrators 8, 9 with a reset, and the inverting inputs - to the output of the analog switch 1, the inverted control input which is connected to the output of the comparator 16, the inverting input of which is connected to the zero-potential bus 21, and the non-inverting input to the input bus 20 and the input of the module 17 allocation module.

The phase locking unit 18 in case of overloads can be made on the basis of the D flip-flop 23, the AND-24 element, the inverter 25, the coincidence element 26, the OR element 27, the output bus 28, the first input bus 29 and the second input bus 30, while the output bus 28 is connected to the output of the OR element 27, one input of which is connected to the input bus 29 and the first input of the element NE 24, and the other input to the output of the coincidence element 26, the first input of which is connected to the input bus 30 and the input of the inverter 25, and the second input - with the inverse output of the D-flip-flop and the second input of the IS-NOT element 24, t The rety input of which is connected to the output of the inverter 25 with the clock input of the D-flip-flop 23, the information input of which is connected to the bus 21 of zero potential, and the input of the unit to the unit - to the output of the element AND-24 24.

Analog switch 1 can be made on the basis of a 590KH4 chip, comparators 6, 7, 16 - on the basis of 521 САЗ microcircuits, RS-triggers 14, 15 - on the basis of a 533TP2 microcircuit, elements OR 4, 12, 13, 27 - on the basis of a 533 microcircuit LL1, counting trigger - based on 533 TB6 microcircuit, formers 2, 3 pulses based on microcircuit 533 АГЗ, D trigger 23 - based on 533 ТМ2 microcircuit, element IS-HE 24 - on the basis of 533 LAZ microcircuit, inverter 25 - on the basis of the chip 533 LI1, the element 26 matches - on the basis of the chip 533 LI1. Allotment unit 17

the module can be fully alongside an opamp with diodes in a feedback circuit, a voltage source 5 on the basis of an EN1 circuit 142 or an op amp with a stabilizer in the input circuit, a sum amplifier 19 on an op amp, integrators 8, 9 with reset - on operational amplifiers with capacitors in the negative feedback circuit and analog switches, such as 590 ELF, connected in parallel to the capacitors, and the generator 11 clock pulses - based on the chip 1006 VI.

Phase pulse converter works as follows.

The clock pulse generator 11 generates short pulses with a period of following T, which is fed to the input of the counting trigger 10. At the forward and inverse outputs of the trigger 10, two sequences of pulses are formed, having a 2T following period and shifted in phase by 180 °. The pulse sequences from the direct and inverse outputs of the counting trigger 10 arrive at the reset inputs of the integrators 8 and 9 and at the inputs of the OR elements 12 and 13, respectively. The other inputs of the elements OR 12 and 13 receives a signal from the output of the generator 11.

At the same time, from the outputs of the OR elements 12 and 13, low-level signals are input to the inputs of the installation at zero of the flip-flops 14 and 15, respectively. The leading edges (the differences from one to zero) of these zeroing signals are delayed relative to the leading edges of the signals from the direct and inverse outputs of the trigger 10 for the duration of the generator pulses g.

The inputs of the integrators 8 and 9 receive the reference voltage from the output of the source 5 of the reference voltage. Integrators 8 and 9 work alternately in each clock cycle. If the integrator 8 is in the integration mode in one mode, then the integrator 9 and its corresponding trigger 15 are reset to zero at that time, and in the next cycle their state changes to the opposite, that is, the integrator 9 is in the integration mode, and the integrator 8 14 reset.

At the outputs of the integrators 8 and 9, two sawtooth voltages are formed (lines 8 and 9 in Fig. 3) shifted by period T, which are fed to the non-inverting inputs of the comparators 6 and 7, respectively.

The inverting inputs of the comparators 6, 7 receive the analog voltage from the output of the analog switch 1. The switch 1 controls the signal from the comparator 16. With a positive voltage on the input bus 20 from the output of the comparator 16, a single level signal goes to the control input of the switch 1, and if negative, the signal is zero. Correspondingly, the output of the analog switches 1 in the first case receives a signal from the module allocation unit 17, and in the second from the output of the summing amplifier 19.

As soon as the signal level from integrators 8 or 9 exceeds the signal level from switch 1, then on the inverse outputs of comparators 6 or 7, respectively, a zero-level signal appears, switching RS-triggers 14 or 15 to one state. If, in the presence of interference, the comparators 6 or 7 is switched several times during a period, then the triggers 14 and 15 perceive only the first switching, thereby preventing the formation of several pulses in one period. The shaper 2 and 3 on the differences from a single to a zero level on the inverse outputs of the RS-flip-flops 14 and 15 produce pulses with a duration corresponding to the duration of the signals at the output of the generator 11.

The signals from the outputs of the formers 2 and 3, formed in different periods, are combined on the element OR 4 and fed to the input of the phase fixing unit 18 under overloads, to another input of which the signal comes from the output of the generator 11. The phase fixing unit 18 serves to eliminate the output loss The signal of the converter on the output bus 22 at input overloads (exceeding the value of the input voltage module (UBx) on the input bus 20 is the value of the voltage module of the voltage source (Uo), since in this case the outputs of the driver 2 and 3. The pulses do not form. Therefore, in case of overloads, in order to avoid failure of the phase fixing unit 18, the output bus 22 transmits pulses from the master pulse generator 11. The operation of the phase fixing unit 18 (Fig. 2) during an overload is shown in the timing diagram ( Fig. 4) and is as follows.

The initial setting of the D-flip-flop is not required, since immediately after the end of the first pulse (from generator 11) on the input bus 30 of the D-flip-flop 23 it is set to a cool state, in which a single level arrives at the inverse output NOT 24 and input element 26 matches.

The zero level, which enters the input of the NAND 24 element, prohibits setting the trigger 23 to one for the duration of the input signal. If there was no overload on the 5th input, then during this period between the pulses on the input bus 30, the bus 29 receives a pulse (from the output of the OR 4 element), which through the OR 27 element is output to the output bus 28 of the unit, and also goes to the input of the element AND-NO 24, at the output of which a zero-level signal appears, setting the trigger 23 in one state. The zero-level signal from the inverse output of the trigger 23 is supplied

5 to the input of the coincidence element 26 and prohibits the passage to its output and to the output of the element OR 27 of a signal coming from the generator 11 to the input bus 30 of the phase fixing unit.

0 If an input overload occurred in some period, then the signal on bus 29 does not appear in this period, the trigger 23 remains in the zero state, at which the unit level from its inverse output

5 permits the passage of a signal arriving from the generator 11 to the bus 30 of the block, to the output of the element 26, and then to the output of the element OR 27 and to the output bus 28 of the block of phase fixation during overloads.

Thus, in the event of an overload on the input, the signal on the output bus 22 of the phase-impulse converter is preserved and its operation is not impaired. Under normal conditions, when the voltage of the input control signal on bus 20 is changed in the range of negative values from - Uo to 0 and in the range of positive values from 0 to Uo (Uo is

0, the module of the reference voltage, the delay At the leading edge of the output signal on the bus 22 of the phase-pulse converter with respect to the leading edge of the signal of the master oscillator is determined accordingly by the formula

Al., + .TЈ.

where i is the period of impulses from the generator of equivalent pulses 11;

Uy is the value of the control voltage module on the input bus 20;

Uo is the value of the module of the reference voltage from the output of the source of the reference voltage - 5.

Accordingly, the phase of the output signal in radians relative to the reference in the specified ranges is determined by the formulas

Ay, -2: U ,, Uy: Ayv 2tt.

Thus, the introduction of the second and third element OR, two RS-flip-flops, the third comparator, the module allocation unit, the phase locking unit during overloads and the summing amplifier with appropriate connections into the phase-pulse converter allows to expand the range of input transformed signals and the control range phase of the output pulses, eliminate the disappearance of pulses during overloads, as well as improve noise immunity, which significantly increases the reliability of the phase-pulse signal conversion. i

Claims (1)

Invention Formula A pulse-phase converter containing an analog switch, two pulse drivers, the first element OR, a reference voltage source, the first and second integrators with a reset, the inputs of which are combined, and the outputs are connected respectively to the non-inverting inputs of the first and second comparators, the inverting inputs of which are combined, and a generator clock pulses, the output of which is connected to the input of a counting trigger, characterized in that, in order to broaden the dynamic range and increase reliability, and, the second and third OR elements, two RS triggers, the third comparator, the module allocation module, the phase locking unit of the overload and the summing amplifier, the output of which is connected to the first input of the knowledge switch, are added to it, the first input to the output source of the reference voltage inputs and integrators, and the second input is connected to the second input of the analog switch and to the output of the selection module of the module, whose input connected to the input bus of the converter and to the non-inverting input of the third comparator, the inverting input of which is connected to the zero potential bus, and the output to the inverting control input analog switch, the output of which is connected to the inverting inputs of the first and second comparators, the outputs of which are connected respectively to the installation inputs to the unit of the first and second RS-flip-flops, the installation inputs to zero of which are connected respectively to the outputs of the second and third elements OR, and the inverse outputs through the corresponding pulse shapers to the inputs of the first the OR element, the output of which is connected to the first input of the phase locking unit during overloads, the output of which is connected to the output bus of the converter, and the second input - to the output of the clock generator and to the first inputs of the second and third OR elements, the second inputs of which are connected respectively to the forward and inverse outputs of the counting trigger and inverse r JM reset inputs of the first and second integrators. FIG. 2 22 Vz.3