SU1531195A1 - Device for pulse synchronization - Google Patents

Abstract

The invention can be used in devices of automation and computing. The purpose of the invention is to expand the functionality by ensuring the generation of output pulses from an irregular sequence of clock pulses. For this, a 3 clock pulse generator, a shift register 4 and a coincidence block 5 are used. The device also contains the first and second D-triggers 1 and 2, the first input bus 7, the second input bus 8 and the output bus 9. 1 sludge.

Description

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The invention relates to pulsed tech. E and can be used in automation and computing devices.

The purpose of the invention is to expand the functionality by providing output pulses from an irregular sequence of clock pulses.

Fig. 1 is an electrical functional diagram of the device; Fig. 2 is a schematic of a match block; Fig, 3 is a diagram of the shift register;

FIG. 4 is a diagram of a clock pulse generator; Fig. 5 shows timing charts explaining the operation of the device.

The device for synchronization contains the first 1 and second 2 triggers, each of which is P-type, a generator of 3 clock pulses, a shift register 4, a block 5 of coincidence, an AND-NE element 6, the first trigger 1 being connected to a common bus, the S input is - with the first input bus 7 and with the first input of the block 5 coincidence, the input of which is connected to the direct output of the first trigger 1, the C input of which is connected to the inverse output of the second trigger 2, the C input of which is connected to the output of the AND-HE element 6 , (PerviyCh entrance is connected to the FJTO swarm by the input bus 8, the second input is connected Inen with the first input bus 7 and with the first input of the block 5 coincidence, the output of which is connected to the D input of the second trigger 2, the direct output of which is connected to its R input and the first input of the shift register 4, the second input of which is connected to the output of the generator 3 clock pulses, the first output - with the output bus 9, the second output - with the S-input of the second trigger 2,

Block 5 matches contains the element AND-NOT 10, the first 11 and second 12 inverters, the output of the first of which is connected to the output of block 5 of the match, the input of the first of which through the second inverter 12 is connected to the output of the element AND-NOT 10, the first input of which is connected to the first input of block 5 coincidence; the second input with the second input of block 5 coincidence.

The generator 3 clock pulses will hold the resistor 13, the inverter 14, the quantum resonator 15, the first 16 and the second 17 capacitors, and the resistor

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13 and a quartz resonator 15 are connected between the input and output of the inverter 14, the input and output of which are connected to the common bus through the first 16 and second 17 capacitors; the clock pulse generator 3 is the output of the inverter 14,

The device works as follows.

Bus 8 receives an irregular sequence of negative sync pulses, the duration of which and the pause between them can vary,

Bus 7 receives a positive signal, the duration of which is significantly longer than the maximum clock pulse duration on bus 8 (FIG. 5a).

If during the action of the signal on the bus 7 to 8 (FIG. 56) there are sync pulses, the trigger 2 is activated and gives a low level on the input; . register 4 shift on the leading edge of the first clock pulse.

Then trigger 1 is set to O, and a high level is generated at the output of block 5, which prohibits repeated triggering of trigger 2 when the following sync impulses are received from the bus in (Fig. 56),

If there is no si} 1x1 ipuls on bus 8 during the signal on bus 7, the end of the last nazyvayut a high level at the output of element 6, the trigger of trigger 2 and the launch of shift register 4.

Inverters 11 and 12 serve to delay and hold low at the D input of trigger 2 after the termination of the signal on bus 7,

The duration of the signal at the output of the flip-flop 2 is determined by the shift register 4, which outputs the set signal to 1 at the S input of the flip-flop 2,

The shift register 4 completes the second clock synchronization of the signal from the output of the trigger 2 by the immersions of the high frequency crystal oscillator 3 and generates an output signal to the bus 9 of a predetermined duration (FIG. 5c),

The feedback to the R input of trigger 2 excludes its switching when the conditions on its D and C inputs change,

Claims (1)

The initial state of the triggers 1 and 2 are set on the S-input, claims A device for synchronizing pulses containing two triggers. 51 each of which is D-type, the D-input of the first of which is connected to the common bus, the S-input to the first input bus, the NAND element, the first input of which is connected to the second input bus, and the output bus, characterized in that in order to extend the functionality due to the generation of output pulses and from an irregular sequence of clock pulses, a clock pulse generator, a shift register and a coincidence unit are inputted thereto, the first input of which Phie. 311956 connected to the first input bus and the second input of the NAND element, the second input to the direct output of the first trigger, the C input of which is connected to the inverse output of the second trigger, the direct output of which is connected to the first input of the shift register, the second input of which is connected to clock generator output 10 The first output is with the output bus, the second output is with the S input of the second trigger, the D input of which is connected to the output of the coincidence unit, the C input with the output of the NAND element. a.I ; { FI.5