SU1529250A1 - Device for dividing analog signals - Google Patents

Abstract

The invention relates to computing and can be used in the construction of automatic transmittance, gain meters and other devices associated with the division of electrical signals. The purpose of the invention is to expand the range of measurements of the relationship of signals with different coefficients of instability. The device for dividing the analog signals comprises a switch 1, a synchronization unit 2, an adder 3, a selective filter 4, a phase-measuring unit 5, a normalization unit 6 and a sensitivity mode selection unit. The introduction of the sensitivity mode selection block allows you to expand the range of measurements of the relationship of signals with different instability coefficients and to make an automatic selection of the sensitivity mode. 5 il.

Description

; The invention relates to computing technology and can be used; during the construction of automatic 1 (1 transmitters of power, power and other devices associated with the division of electrical signals

The aim of the invention is to expand the range of measurements of the relationship of signals with different coefficients of instability.

Fig. 1 shows a block diagram of a device for dividing analog signals; Fig. 2 is a diagram of the formation of a step pulse at the tertiary stage of a ratio measurement; la fig, 3 - dependences of the initial phase Cf on the values of relations C corresponding to different sensitivity modes; Fig. 4 is a functional diagram of a sensitivity mode selection block; Fig. 5 shows an algorithm for its operation.

The device for dividing the analog signals comprises a switch 1, a synchronization unit 2, an adder 3, a selective filter 4, a phase-measuring unit 5, a normalization unit 6, a sensitivity mode selection unit 5 for a single-chip microcomputer 8 and buffer registers 9,

The operation of the device for dividing the analog signals is realized in three stages. First, the input signal divider is constantly fed to the normalization unit 6 and switch 1, for the first time the switch 1, controlled by the sensitivity mode selection unit 7, passes the signal through the synchronization unit 2 -divider to adder 3 during Ti / 2, during: the second time interval equal to: Ti / 2, to the adder 3 through switch 1 receives a dividend signal, passage through block 6 of normalization, In the third time interval, equal to Ti / 2, input; signals on sums Ator 3 does not pass. The time separation process is then repeated. As a result, the output of the adder 3 generates a pair of stepwise-pulse signal presented in FIG. 2, i. The signal from the adder 3 goes to the selective filter 4, tuned to the first harmonic of the generated pulse-shaped signal (FIG. 2) “The initial phase of the selected harmonic is proportional to the ratio of the input signals of the dividend and the divisor

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The phase-measuring unit 5 measures the phase shift between the reference signal from synchronization unit 2 and the output harmonic signal from the selective filter 4. The phase-measuring unit 5 converts the measured phase value into a binary parallel code, which is stored in the mode selection unit 7, the sensitivity. At the second stage, the measurement process is repeated and the subsequent measurement of the phase in the binary code is stored in block 7 of the selection of the sensitivity mode.

At the third stage, the subsequent value of the measured phase t is compared with the previous value of the phase cf in block 7 for selecting the sensitivity mode for the group of m-fallen bits. If the lower bits did not match, then the input signals are unstable and the device continues to operate in low sensitivity mode with Tig 0.67 (FIG. 3). Then, the sensitivity mode selection unit 7 outputs to the inputs of the synchronization unit 2 a control code K corresponding to the difference in the compared values of the initial phases (Cf - 2 °) In turn, the synchronization unit 2 changes or keeps the sensitivity of the device by changing the durations of the cycles (steps) to divide depending on the value of the control code K. The device then measures the signal ratio in the optimally selected sensitivity mode and gives the final measurement result, after which It compares the re-entered values of if and c. If these values match, then the value of K decreases by 1 and the sensitivity increases, otherwise, K increases by 1 and the sensitivity decreases. In the third stage, the nonlinear correction for Tig 0,67 is also adjusted using N values the normalization code received at the control input of the normalization unit 6, at the output of which a signal of the form XX + is formed

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not on multiplying digital-to-analog converter, converter, current - voltage and shaper of signal difference.

Thus, the sensitivity of the dividing device is in

Unit 6 may be inversely dependent on the value of the control code K generated on the control outputs of the sensitivity mode selection unit 7.

FIG. 5 is a block diagram of the operation of the device, where the previously described first and second stages of operation of the device are shown by block 01. The remaining blocks describe the third stage of operation of the device.

One of the variants of the circuit implementation of the sensitivity mode selection block 7 is shown in FIG. A and consists of a single-chip microcomputer 8 and buffer registers 9. The information inputs of block 7 are represented by a sixteen-bit bus indicated in FIG. 4- The normalizations are performed in the input of the eight-bit bus, designated Vk, nf,. The beats of the sensitivity control code of the sensitivity mode selection unit are made in the form of a four-bit bus, labeled Ex. out ,, and the sync input is labeled upr, input,

Claims (1)

Invention Formula A device for dividing analog signals, comprising a switch connected by a first information input to an input of a set divider signal and the first information input of the normalization unit connected by the second information input to the input of the signal-divisible device, and the output to the second information input of the switch connected by the control inputs to the first and second outputs of the synchronization unit, and the first and second outputs to the input The cymes of the motherboard, the output of which is connected to the input of a selective filter connected to the information input of the phase-measuring filter, the input voltage of which is connected to the third output of the synchronization unit, In order to expand the measurement range of the ratio of signals with different instability factors, a sensitivity mode selection block is added to it, connected by an information input to the output of the phase-measuring unit, a synchronizing input - to the fourth output of the synchronization unit, and the output of the normalization code - to the input control of the scaling factor of the normalization unit, and the output of the sensitivity control code, to the control input of the pulse duration of the synchronization unit. l Tul2 Ty Tul2 FIG. 2 fig 1 1 G out info Fy HaLfcf / 7a Jl. not 07 del