SU1515359A1 - Frequency-phase detector - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency-phase locked loop systems. The frequency-phase detector contains a two-pole source of 3 reference voltages, keys 6–8, generator 4, unit 5 for sampling and storage, driver 1 for control pulses of a frequency difference converter. Introduction to the frequency-phase detector of the driver 2 of the pulses controlling the transformation of the phase difference and the key 9 made it possible to expand its functionality by shaping the output voltage depending on the phase difference of the input signals. 3 il.

Description

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The invention relates to a pulse technique and can be used in frequency-phase auto-frequency systems.

The aim of the invention is to extend the functionality by shaping the output voltage, depending on its difference on the phase difference of the input signals.) 0

Figure 1 shows the functional diagram of the frequency-phase detector; 2 and 3 are timing charts of its operation.

 The lacTOTHo-phase detector contains 15 shaper 1 pulse control converting the frequency difference, a forgor world 2 and a control switch for converting the phase difference, a two-pole source 3 reference voltages, 20 integrator, block 5 sampling and storage, keys 6 - 9 and output buses 10 and 11 of a bipolar source of 3 reference voltages, while the output bus 10 of the source of 3 reference voltages is connected via key 6 to the first input of the integrator A, and the output bus 11 of source 3 of the reference voltages and fourth

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connected to the input of block 5, selection 1: and storage, the output of which is connected to the output bus and via switch 8 to the third input of the integrator 4, and the inputs of the driver 1 of the frequency difference control impulses are connected to the input buses, the first output to the control the input of the key 6 and the first input of the driver 2 of the control pulses of the phase difference conversion, the second output with the control inputs of the keys 7 and 8, and the third output with the control input of the sampling and storage unit 5. The control input of the switch 9 is connected to the output of the generator 2 of the control pulses of the phase difference conversion, the second input of which is connected to the second input of the driver 1 of the control pulses of the difference of the frequency difference. and 18, the resistor 19 and the capacitor 20, while the C-in trigger of the trigger 12 is connected to the input bus 21 of the device, the inverse output to the C-input of the trigger 1 and the first terminal of the II-II element 17, and the direct output

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with the first input of the element IS-HE 18, the second input of which is connected to the direct output of trigger 1 and the second input of the element IS-NOT 17, the output of which is connected to the C-inputs of the flip-flops 15 and 16. The direct output of the trigger 15 is connected to the common bus through connected in series resistor 19 and capacitor 20, the combined outputs of which are connected to the R-input of the trigger 15, the direct output of which is connected to the S-input of the trigger 1b, the output of which is connected to the R-input of the trigger 13, C- the input of which is connected to the second input bus 22 device. The first output of the frequency difference conversion driver 1 is connected to the output of the NAND element 18 and the output bus 23, the second output to the direct output of the trigger 13 and the output bus 2, and the third output from the AND-NE 17 element and the output bus 25 .

Shaper 2 pulse control converting the phase difference can be performed on the trigger 2b and the element AND NOT 27, the output of which is connected to the control input of the key 9. And the inputs to the bus 23 and the output of the trigger 2b, the C input is connected to the bus 22 of the device .

The integrator can be implemented on an operational amplifier 28 with a capacitor 29 in the negative feedback circuit and summing resistors.

30 - 33 at the entrance.

Sampling and storage unit 5 can be performed on a connected key 3, a resistor 35 and a capacitor Zb, the combined-outputs of the latter are connected to the repeater input on the operational amplifier 37, while the control input of the key 3 is connected to the bus 25, the input of the key 3 - with the output of the integrator Ts, the second output of the capacitor Zb - with a common bus, and the output of the amplifier 37 - with the output bus of the device.

Consider the operation of the detector when applying to the bus 21 pulses of the reference frequency f, and to the bus 22 - pulses of the adjustable frequency - f. Work depends on the ratio of frequencies. Fig. 2 shows diagrams for the case of the equality of frequencies: corresponding to the synchronization in the system of frequency-phase auto-tuning (PFLP).

The pulses on the bus 21, which follow with frequency f, (Fig. 2, Of), / are emitted by 2 trigger 12 (Fig. 2.5), on the positive switches of the output voltage of which trigger switches 1 (FIG. 2, c). The period of this voltage, the duration, A / f, sets the cycle time corresponding to the interval t,.,., T (Fig. 2.7). At the output of the element 17, periodic pulses are selected that control the sample (Fig. 2), their temporary position corresponds to the interval U tpt, in the first cycle of duration T, 1 / f. At the output of the element 18, an emma is allocated (pulse pulses of the same duration T, 1 / f, carrying information about the frequency f, the time position corresponds to the interval U t, t, in the first cycle (FIG. 2, e). For selection of intervals that carry information about the pulse frequency fj, triggers 13, 15 and 16 are used. By a positive difference in the output voltage, element 17 is generated at the output of trigger 15 in each cycle a short pulse is formed (Fig. 2). trigger 1b has been set to zero, with the voltage on its forward It had a low level corresponding to O. Accessing the R input of the trigger 13, this voltage prevents it from switching. When the pulse arrives at the S input of the trigger 1b, the latter switches to 1, the blocking of the trigger 13 stops, it starts to switch impulses and , arriving by them on the C-input of the flip-flop 13. After the second switch on the output of the flip-flop 13, a positive voltage drop is formed (Fig. 2, i), under which the flip-flop 1b returns to the initial zero position at which the flip-flop 13 is blocked. As a result, at the output of the flip-flop 13, pulses of duration, are formed, carrying information about the frequency f, them. temporary position corresponds to interval 3 of the first cycle. Phase intervals are separated by shaper 2. Pulses from bus 22, arriving at the C input of the trigger 26, switch it, causing the formation of a square voltage (Fig. 2, k), which enters the input of the element 27, to another input the voltage comes from the output of the element 18 for

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worldviewer 1. At the output of the 1smith 27, pulses are formed, the time position of which corresponds to the phase interval I in the first cycle. Their frequency is half the maximum possible.

Under the action of control pulses, the recharge currents of the integrator capacitor flow, which causes forcing the integrator output voltage. In the U interval, the first cycle is unlocked by key 6, in the interval I, keys 7 and 8, d- in I-, H- interval 1 - key 9. This causes flow of recharge currents; in the interval и, - current Ij ,, U 01 / F,., flowing in the circuit of the first input under the action of voltage G (,, output 11 cost 3, in the interval 1) t - current I p, -U (, / P ,, flowing in the second input circuit under the action of a voltage — U c., Output 10 of source 3 and feedback 1 rb.e. I-BH —cc flowed from the third input circuit under the action of the output voltage of the detector, in the interval IU of current 1 oz o7 / 3 Le R ,, P.,, G ,, and ROC resistances of ES, 31, 33 and 32 resistors, respectively. For the diagrams of Fig. 2, the roBani forms — p; eb, and the integrator in the second and later |, their cycles occur analogue In the interim U, when the recharging currents are absent, the integrator voltage does not change, the graph (Fig. 2, m) has a flat section, the assembly takes place, the switch 3 is unlocked from the bus 25, the capacitor 36 is charged to the maximum the values of the output voltage of the integrator, and through the amplifier 37 this voltage goes to the output of the detector,

The scheme works with f. T f by c Rets with the help of diagrams of fig. 3 for the case f, f. The detector is designed for operation at a frequency ratio of i - / i, 70.5.

Formation of time intervals

Up and r, of duration i, f.l / f, are produced by the triggers 12 and lA and by the logic elements 17 and 18, just as in the previous case. The duration of the conversion cycle is still equal to.,. However, the temporal position of the intervals of pre-duration U j, in contrast to the previous one, varies from cycle to cycle, and the interval Uj, of each cycle, when the integer voltage does not change, is used for the sample.

The maximum sign of the integrator voltage and the output voltage of the detector (Fig. 3, n) also vary from cycle to cycle. If the frequency difference is small, the output voltage has a variable triangular shape. As a result, a voltage is formed at the detector output, having two components, one of which depends on the frequency difference, the other on the phase difference. The installation signal in the O flip-flop 1b is used in the case when, due to the large duration of the interval U, the flip-flop 13 does not have time to switch in time.

The proposed frequency-phase detector exceeds the speed known. This allows its use to improve the quality of PFAP systems. Its speed in converting the frequency difference and phase difference is almost the same as when using separate frequency and phase detectors. The Mf / P system with the proposed detector has the same characteristics as the system containing both detectors and an adder. In this case, the application of the proposed device allows to reduce the volume of CFMF, simplify the design and increase the reliability of the CFL system as a whole.

Claims (1)

Invention Formula Frequency-phase detector containing a bipolar reference source five 0 5 five voltage, the first output of which is connected via the first key to the first input of the integrator, and the second output through the second key - to the second input of the integrator, the third input of which through the third key is connected to the output bus and the output of the sampling and storage unit and the driver of the control pulses of the frequency difference conversion, the inputs of which are connected to the input buses, the first output — to the control input of the first key, and the second output — to the control inputs of the second and third keys, distinguishing In order to expand the functionality, the phase difference control pulse generator and the fourth key are additionally introduced, the first input of the phase difference control pulse generator is connected to the first output of the frequency difference control pulse generator, the second input is from the second detector input bus, and the output with the control input of the fourth key, the input of which is connected to the first output of the bipolar reference voltage source, the output - to the fourth input of the integrator, and the control input of the sampling and storage unit is connected to the third output of the frequency difference former control pulse generator.