SU1513434A1 - Device for shaping digital sequences - Google Patents

Abstract

The invention relates to computing technology and can be used in programmable timers and synchronization systems. A distinctive feature of the device is that it allows you to expand the range of formation of the frequency division factors. The maximum division factor in the device is equal to the product of the capacities of the first 1 and second 5 counters. Changing the parameters of the output digital sequences of the device is provided by reprogramming the first 2, second 3 and third 7 blocks of memory without making circuit changes. The aim of the invention is to expand the scope by increasing the range of generated frequencies. The goal is achieved by the introduction of blocks of 3.7 memory, an element of OR 6. 1 Il, 1 tab.

Description

f ... f f ... f ... f f f

O1

00

4 co 4

V

M-K-tm- t

315

The invention relates to computing technology and can be used in programmable timers and synchronization systems.

The purpose of the invention is to expand the field of application by increasing the range of generated frequencies.

The drawing shows a block diagram of the device.

The device contains a counter 1, memory blocks 2 and 3, a register A, a counter 5, an element OR 6, a memory block 7, outputs 8, a clock input 9.

The device works as follows.

Counter 1 counts the input clock pulses and provides a sequential loop through the addresses of the first memory block 2. This causes the appearance of a digital sequence at each of its k outputs with parameters determined by the information recorded on this bit. These digital sequences are sent to the address inputs of memory block 3, in cells of which, for each bit, there are recorded counts of logical zeros and ones, ensuring that any i-rq output performs the logical ratio I

i Y; ... LH, (1) 1 where x, x, ..., x - digital sequences

on any n of its k inputs; y, - output digital sequence,

; Thus, under the condition of the coincidence of: the duration of the pulses of the digital: 1.2 series sequences, ...,.,: The inputs of memory block 3, at its ith output, a digital sequence is formed with a period T equal to the smallest common multiple periods T, .T, ..., T digital sequences on any of its inputs .1,2, ..

:

; To obtain, for example, T g |, iti and the presence at the outputs of a .12 memory block (i.e., at the address inputs (memory block 3) of digital sequences with periods T and tC-2 yi T, it suffices to write in the cells of the latter at the addresses according 3 34V

but the table is logical 1 in the i-th bit.

The list of addresses x ... x ,, of a block with 3 memories corresponding to Y;

 X., L 2 Vl: UCH "Xj, E b

given in the table. .

0

five

0

five

In order to obtain; for example, T, - 70lT in, with the presence at the outputs of block 2 of memory T, 5 T Tz,

Overhead line

T2 -7 t

er

And Te 5, j (it suffices to write logical 1 in cells with the addresses marked in the table, in the J-M bit de Yj of block 3 of memory).

Thus, additional denominations of division coefficients are formed at the outputs of memory block 3, which differ from the division factors from the outputs of memory blocks 2 and 7, which makes it possible to expand the number of simultaneously generated divide factors at the same hardware costs, or it gives the opportunity to have the best reliability indicators for each dividing ratio being formed.

At the first output of the memory block 3, a digital succession is formed30

35

40

This determines the counting cycle of the counter 1 and is the input for the counter 5. As its pulses arrive at the counting input of the counter 5, the process of forming digital sequences at the outputs of memory block 7, similar to the formation of digital sequences at the outputs of block 2 ti.

Digital sequences from the outputs of blocks 2, 3, and 7 of the memory are fed to register 4, where they are temporarily assigned to the front edges of the input signal.

The period of the output .digital sequences of the device with integer coefficients p can be represented as

Tbyi R Tech. (2) In practice, the coefficient p can vary from a few to 50 and is represented in the decimal number system as

R . + +.

, + 1 -10

(3)

55 In an arbitrary number system with base L, the coefficient p can be represented as

p + a, +.,. +.

(four)

 . The device is a scheme for realizing the formation of a river by the formula () n 1 and calculating the value of p, which is the smallest common multiple of the numbers p, p,, ...,.

R F (P ,, PZRP), (5)

de F (p, p

P) - the smallest common multiple of P

RPV 5; for every 10 r d i d i o you w i s w h o h t h t h t h t h h t h h t h t h h t h h t h t h h t h t h h t h t h h t h h t h t h h t h h t h t h h t h h t h up to 50 min 50 count and 55 digits resp. and resp 1 value

20

25

In this case, in block 2 of the memory, in the corresponding bits, digital sequences are formed, corresponding to the coefficients p, p, ..., p according to formula (2), not exceeding the cycle of counter 1, and formula (C),

In block 7 of the memory, numerical sequences are formed corresponding to the coefficients, ..., RP, multiples of the counter 1 counting cycle, and the value a agrees to the formula (4).

At the first output of memory block 3, a digital sequence is formed according to the formula (5), defining the counting cycle of the counter 1, i.e. the base of the number system is L, equal to the smallest common multiple p, P, ... p. In the same way, a digital sequence is formed at the m output of memory block 3, which determines the zeroing cycle of the entire device.

The device forms two scales for setting the time parameters of digital sequences - (according to (4) with n 1). The exact position of the pulses is given by the data in memory block 2, coarse - in block 7. So, for example, to form a digital sequence y-with p 540 401 (500 ° + 1. "500 at the base of the L .500 is enough in one from the bits of both the first 2 and third 7 memory blocks, write logical 1 to cells at addresses 40, respectively (Aj and 1 (A,), and in the second memory block 3, write information satisfying the logical relation

10 45 50 55

thirty

35

40

deh.

W; .

X.

AO

- inputs of the second memory block connected to the corresponding outputs of the first 2 and third 7 memory blocks.

20

25

five

6

Claims (1)

Apparatus of the Invention A device for generating digital sequences containing 5; two I counters, a first memory block and a register, the counting input of the first counter being connected to the register recording enable input and a device clock input, a group of distant outputs of the first counter connected to the group of address inputs of the first memory block, whose outputs are from the first to the Kth, where K is the number of outputs of the first device sequence, are connected respectively, from the first to the Kth information, the register inputs, output the first to the Kth are the outputs of the first to the Kth first sequence of the device, respectively, characterized in that, in order to expand the scope of application i by increasing the range of generated frequencies, the second and third memory blocks and the element are entered into the device OR, with the outputs of the first Lam al block from the first to the K th connected to the | address inputs of the second memory block, respectively, from the first to the K th, the first output of the second memory block is connected to the counting input of the second counter, to the first input of the OR element, with (K + 1) th the information input of the register, the outputs of which from (K + 1) -th to t-th, where m is the number of outputs of the second sequence of the device, are outputs respectively from (K + 1) -th to t- (. the second sequence of the device, the outputs of the second memory block from the second to (t-1) -th connected to the information inputs of the register, respectively (K + 2) -th to (t-1) -th, t-th output of the second memory block ti is connected to the reset input in O 5 of the second counter, with the second input of the OR element and with the m information input of the register, the output of the OR element is connected to the reset input in O of the first counter ,. the bit outputs of the second 0 counter are connected to the address inputs of the third memory block, the outputs of which are from the first to the 1st, where G is the number of outputs of the third sequence of the device, are connected to the address- 5 inputs of the second memory block, respectively () along the (K + 1) st and with the information inputs of the register, respectively, c. (t + 1) -th through the 1st, where 1 is the number of outputs of the third consecutive five 0 the device, the outputs of which from (t + 1) th to 1st are outputs go  15134348 accordingly, the (t-1) th to thirtieth sequence of the device.