SU1510081A1 - Device for measuring setting time of output signal of d-a converters - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be used in systems for controlling dynamic parameters of digital-to-analog converters / DACs /. The purpose of the invention is to increase the speed of the device by reducing the measurement time of the establishment of the output signal of the controlled DAC. To do this, in the device for measuring the time of setting the output signal of the DAC, which contains setters 1 and 2 of codes, switch 3, generator 4 clock pulses, RS - trigger 5, first driver 6 pulses, elements 7-8, reversible counter 9, DAC 10, adder 11, driver 12 of different polarity threshold levels, two-threshold comparators 13 and 14, comparators 15, 16, D-trigger 21, pulse counter 22, input bus 24 and output bus 25 for connecting a test DAC 26, two generators 18 and 19 are entered linearly varying voltage, second driver 20 pulses, comparator 17 and register 23. 2 Il.

Description

The invention relates to electrical engineering and can be used in automated systems for monitoring the dynamic parameters of digital-to-analog converters (DAC).

The purpose of the invention is to increase the speed of the device.

In FIG. 1 shows a functional diagram of the device ·, in FIG. 2 timing diagrams of signals explaining the measurement principle.

The device contains switches 1 and 2 codes, switch 3, generator 4 pulses, RS-trigger 5, the first driver 6 pulses, elements And 7 and 8, a reversing counter 9, digital-to-analog converter (DAC) 10, adder 11, driver 12 20 different polar threshold levels, two-threshold comparators 13 and 14, comparators 15-17, generators 18 and 19, linearly varying voltages (GLIN), the second driver 20 pulses, 25 D-trigger 21, counters 22 and 23 pulses, register 23, output 24 and input 25 bus for connecting a controlled DAC 26.

In FIG. Figure 2 shows the signals: a exponential end portion of the signal of the controlled DAC; b - the first two-threshold comparator 13; in - the second two-threshold comparator 14; g - the first clay 18 with a steepness of about, and the second clay 19 with a steepness of _r .

The device operates as the next counter counter 9. Upon receipt of a start pulse, trigger 5 switches to the Log state. 1 on $ its direct output, element And 7 closes, counter 22 pulses is reset, driver 20 generates a pulse confirming the zero state of CLIN 18 and 19. At the same time, IQ starts driver 6. Element

And 8 is blocked for the duration of the pulse shaper 6, and through the switch 3 to the DAC 26 is connected. source code N, for a given time. (5 After the end of the pulse of the shaper 6 on the bus 24, the N, - * N ^ codes change, the controlled process of switching the DAC 26 begins, the pulses of the generator 5 through the And 8 element begin to arrive at the C-input of the pulse counter 22. When the DAC signal (it free component, since the forced component - the steady signal is compensated) in the zone ± U ₍ (Fig. 2a) comparator 13 is triggered (Fig. 26), the CLIN 18 is triggered (Fig. 2d), and when it gets into the zone ± U ₂ the comparator is triggered 14 (Fig. 2c) and starts 30 clay 19. At the time of achievement of the equalities CLAYS signals 18 and 19 of comparator 17 is triggered, runs generator 20 through D-flip-flop 21, the pulse counter 22 is written into the code register 23. After filling the trigger 5, the pulse counter 22 is reset, the device is ready for the next measurement cycle.

at once.

In the initial state, triggers 5 and 21, counters 22 are reset. In the code generator 1, the code N <is written, in the code generator 2 - code N _e - for the case of control _{3 3st} when changing the codes N, -> N _z . Through the switch 3 to the DAC 26 is connected to the code N ₂ . Steady signal 'DAC 26 is compensated automatically grammed by the action of DAC 10 through sforsignala elements 9-11, 15 and 16. When the signal enters the adder 11 after compensation CD _cr DAC 26 DAC signal 10 in zone ₀ and ± <0.5 photon - 0.511 <U ₄ <U, both comparators 15 and 16 assume a zero state, and counter 9 is disabled. Despite the arrival of the pulses of the generator 4 through the And 7 element at the counting input, the compensation signal code is stored in

Claims (1)

Claim A device for measuring the settling time of the output signal of digital-to-analog converters containing $ 4, two code adjusters, a switch, a clock generator, an RS-flip-flop, a first pulse shaper, two AND elements, a reversible counter, a digital-to-analog converter, an adder, a generator of 50 polar threshold levels., two two-threshold comparator, two comparators, D-flip-flop and a pulse counter, whose overflow output is connected to the R-input of RS-trigger input ⁵⁵ setting the 0 combined with the S-input of RS-latch and YaV is launched by the Start bus, and the counting input is combined with the counting input of the D-flip-flop and connected to the output of the first AND element, the first input of which is connected to the direct output of the RS-flip-flop and connected through the first pulse shaper to the control input of the switch and the second input of the first And element, the third input of which is combined with the first input of the second And element and is connected to the output of the clock generator, jq the output of the second And element is connected to the counting input of the reverse counter, and the second input is connected to the inverse output of the RS flip-flop, the outputs of the code adjusters are connected, respectively, 15 to the first and second groups of inputs of the switch, the outputs of which are the output bus for connecting the verifiable digital-to-analog converter, the outputs of the driver of differently polarity threshold levels from the first to the fourth, are paired with the first and second inputs of the reference voltages of the first and second two-threshold comparators, respectively, and the fifth 25th sixth outputs are connected respectively to the first inputs of the first and second comparators, the second inputs of which are connected to information inputs of the first and second two-threshold to the comparators and are connected to the output of the adder, the first input of which is the input bus for connecting the verified digital-to-analog converter, and the second input is connected to the output of the digital-to-analog converter, whose inputs are connected to the corresponding outputs of the reversible counter, the inputs of the direct and inverse accounts of which connected respectively to the outputs of the first and second comparators, characterized in that, in order to increase the speed, two generators are introduced a linearly varying voltage generator, a second pulse shaper, a third comparator and a register, the outputs of which are the output bus, information inputs are connected to the corresponding bit outputs of the pulse counter, and the recording input is connected to the output of the D-trigger, the D-input of which is connected to the set inputs at 0 the first and second ramp generators and is connected to the output of the second pulse shaper, the first input of which is the Start bus, and the second input is connected to the output of the third comparator a, the control input of which is connected to the output of the second two-threshold comparator, and the first and second information inputs are connected to the outputs of the first and second generators of ramp voltage, the start inputs of which are connected to the outputs of the first and second two-threshold comparators, respectively. Fie. 2