SU1506564A2 - Identifier of channel activity in delta-modulation system - Google Patents

Abstract

This invention relates to the field of radio engineering. The purpose of the invention is to improve accuracy by allowing detection of slowly varying analog signals. The detector contains an instantaneous signal detector consisting of a D-flip-flop 1 and a comparison unit 2, as well as a summing counting unit consisting of a reversible counter 3 and an inverter 4. A frequency divider 5 and a switch 6 are entered into the summing counting unit which includes the two elements AND 7.8, the element OR 9, the inverter 10. The choice of the coefficients. dividing the N divider 5 and the threshold value on the counter 3, specified by connecting to the higher bits or the transfer output of the counter 3, determines the accuracy of detecting channel activity at a certain level of acoustic noise and the corresponding detection delay.

Description

The invention relates to radio engineering and is an improvement of the invention according to the author. St. No. 1363506.

The purpose of the invention is to improve accuracy by providing detection of slowly varying analog signals.

The drawing shows a structural electrical circuit of the channel activity detectors in a system with delta modulation.

The channel activity detector in the delta-modulated system contains an instantaneous signal detector consisting of a D-flip-flop 1 and a comparison unit 2, as well as a summing counting unit consisting of a reversing counter 3, an inverter 4, a frequency divider 5, a switch 6 ,

which includes the first element AND 7, the second, element AND 8, element OR 9, an additional inverter 10. The channel activity detector in the delta-modulation system works as follows.

The controlled information signal is fed in parallel to the input of the D-flip-flop 1 and to the second input of block 2 with its own clock frequency. The output of block 2 is connected to the control direction of the counting input of the reversible counter 3, the counting input of which receives either clock pulses through the circuit element AND 7 - element OR 9 - inverter 4, or pulses with a frequency, n times less than clock, along the circuit divider 5 - element And 8 SP

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the element OR 9 is the inverter A, since the D-flip-flop 1 is an element of the delay per clock, in the case of the unambiguity of the values of the incoming and previous characters of the controlled delta-modulated sequence, a signal (logical unit) appears at the output of block 2, which determines the positive counting direction in the reversible counter 3 and provides for scaling: clock pulses to the counting input of the reversible counter 3 (element 7 and open, element 8 and 8 are closed due to the presence of an additional inverter 10).

The reversible counter 3 records the number of clock pulses during which unambiguous information took place (for example, 0000 ... or 1111 ...).

In the case of ambiguity of the values of the incoming and previous characters (for example, a pause of the combination 101010 ...), a signal (logical zero) appears at the output of block 2, which determines the negative counting direction in the reversing counter 3 and ensures the passage of pulses with a frequency less than the clock, on the counting input of the reversible counter 3 (the element And 7 is closed, the element And 8 is open).

Thus, in the reversible counter 3, the accumulated number decreases with a frequency that is n times lower than the rate of increase (addition) corresponding to the moments of unambiguous

characters in a delta-modulated sequence.

As soon as the number written in the reversible counter 3 exceeds a predetermined threshold, it is decided to detect the channel activity in the delta-modulation system. The choice of the division factor n of the divider 5 and the threshold value on the reversible counter 3, specified by connecting to the higher bits or transfer output of the reversible counter 3, determines the accuracy of detecting channel activity at a certain level of acoustic noise and the corresponding detection delay.

In order to avoid overflow of the reversible counter 3, both with a positive score and a negative count, it can provide an overflow scheme,

with

Claims (1)

Invention Formula The channel activity detector in the system with delta modulation according to aut. St. No. 1363506, characterized in that, in order to increase accuracy by ensuring detection of slowly varying analog signals, series-connected frequency divider and switch are introduced into the summing counting unit, the output of which is connected to the input of the inverter and the second and third inputs are connected respectively to the input the frequency divider and the control input of the reversible counter; the input of the frequency divider is the clock input of the summing counting unit. rLJ