SU1497725A1 - Pulsed variable-delay device - Google Patents

Abstract

The invention relates to a pulse technique and can be used to form an adjustable pulse delay in a wide range. The purpose of the invention is to increase the range of adjustable delay while improving accuracy - achieved by additionally introducing triggers 5-7, counters 8.9, AND-NE elements 10.11, OR-NOT 12-15 elements, generator 16, driver 17. In addition, the device contains a comparator 1, a voltage divider 2, a time setting RC circuit 3, a trigger 4, an input 18 and an output 19 bus. The device provides, in comparison with the prototype, with the same values of RC circuit parameters an increase in Kd times the pulse delay time, where Kd is the division ratio of the counter 8. At the same time, the generated delay does not depend on the frequency value of the generator 16, i.e. . Generator parameter requirements can be relaxed while ensuring high accuracy of the device as a whole. 1 il.

Description

4 h |

vj to

SP

The invention relates to a pulsed technique and can be used to form an adjustable imimage loop delay in a wide range.

The purpose of the invention is to increase the range of adjustable pulse delays while improving the accuracy due to the additional introduction of two counters, three triggers, a generator, two AND-NOT elements, four OR-NOT elements, and a driver.

The drawing shows a functional diagram of the device.

The device contains a comparator 1, a voltage divider 2, a time specifying the HC-circuit 3, triggers 4-7, counters 8 and 9, elements AND-NOT 10 and 11, elements OR-NOT 12-15, generator 16, driver 17 , input 18 and output 19 tires.

The device input bus 18 is connected to the inputs of the voltage divider 2, to the time of the master circuit KS circuit 3 and to the first input of the AND-NE element 10, the second input of which is connected to the inverse output of the trigger 4, p c My output of which is connected to the first input an OR-NOT 15 element whose output is a sub-key to control the input of the generator 16, the output of which is connected to the counting input of counter 8 and the first input of the element OR-NOT 14, the second input of which is connected to the inverse output of the trigger 7, and the output to the second the input element OR NOT 13, the first input of which is connected to output element IPI-NOT 12.8 output -to the counting input of the counter 9, the output of which ow in; Ate output 19 device. The output of the voltage divider 2 (middle point) is connected to the first input of compressor terminal 1, the output time of the master CS-cement 3 (middle point) is connected to the second input of comparator 1, the output of which is connected to a single trigger input 4 through the driver 17. Third dividers The voltage and time of the master RC circuit are connected to the common bus. The output of the counter 8 is connected to the first reset input of the trigger 5, to the single input of the trigger 6 and the first input of the OR-NOT 12 element, the second input of which is connected to the inverted output of the trigger 6. The output of the AND-10 element is connected to the single input of tri-ger 5 and the first input of the NANDI element 11, the output of which is connected to the trigger input 7, and the second input to the forward output of the second trigger 5, the reset input of the trigger 7 and the second input of the element OR 15.

The reset inputs of the flip-flops 4 and 6, the slits 8 and 9 and the second reset input of the flip-flop 5 are connected to the device installation bus in the initial state (not shown).

The device works as follows.

In the initial state, triggers 4-6 and counters 8 and 9 are set to state o.

Signal 1 from the element OR NOT 15 holds the generator 16 in the Vg. Switch. State. Signal O from trigger 5 keeps trigger 7 in state O The circuit is in standby mode.

When the input signal arrives at level 1, the voltage appears at the first and the comparator, the value of which is determined by voltage divider 2, the capacitor time of the master circuit 3 starts, and the trigger 5 switches to one state through the AND-NE logic element 10 which, through the element OR NOT 15, starts the generator 16.

The trigger 6 does not switch due to the signal on the output of the element AND-NOT 10, which enters the input of the element AND-NOT 11, and blocks the passage of the generator pulses to the second counter 9 through the element OR NOT 14. The pulses from the generator 16 are fed to the first counter 8. After the capacitor sets the time. The RC circuit is charged to a level at which the voltages at the inputs of the comparator 1 are compared with, the latter switches and the signal from the driver .17 enters at the input of the trigger 4, switches it to the unit state , which leads to a fixation of the logical level at the output of the element OR-NOT 15, thereby confirming the resolution of the generator, and to the appearance of signal 1 at the output of the element IS-NOT 10, which through the element IS-NOT 11 switches the trigger 7 into one state, thereby allowing the passage of generator pulses in the second counter 9.

By filling the counter 8, the signal from its output switches the trigger 5 to the zero state, and the trigger 6 to one 5U

The signal O from the output of flip-flop 5 switches the flip-flop 7 to the null state, which prevents the impulse from passing from the generator to the second counter 9 through the OR-NOT 1A element. The first output impulse from counter 8 to counter 9 does not pass due to the presence of the element OR NR 12. The generator 16 pulses with frequency ff arrive at counter 8. The frequency of the signals at the output of the counter is equal to fr / 2, where n is the width of the counter 8. These signals through the OR-NOT 12 and 13 elements arrive at the input of the counter 9. After the counter 9 is completely filled, the output signal is formed at the output 19 of the device.

During the charging time of the capacitor, the time of the driving RC circuit to the counter 8, the number of pulses

N,

f f

I r

Otherwise

TV K ,. Tr + Kjt Kj-t + Tr (K, + 1) where T is the period of the pulse generator.

When choosing the parameters of the scheme in such a way that t 7 Tr and K q 1 (the second term of the sum can be neglected), then

Tv

The proposed device provides, in comparison with the known increase in K times the delay time of the pulses while allowing its adjustment by changing the parameters t (i.e., R, C, K). In this case, the generated delay does not depend on the value of the frequency of the generator 16, i.e. Requirements for generator parameters can be relaxed while ensuring high accuracy of the device.

where t is the charge time of the capacitor until the moment when the comparator is triggered, equal to

t - € InK, where O is the constant charge of the RC circuit 3,

equals

 R C;

TO

- the division factor of the divider 2 voltage, K R2 / (R / R,).

After switching the comparator 1 until the signal appears from the output of the counter 8, the counter N will write the number N, which is equal to

N.

 2 Nme- N ,,

where the maximum capacity of the counter 8 is equal to N 1. The time of the output command is equal to

Ty T + T

V

where then - time to first filled

counter 8, equal To-g-;

T - time to fill the counter T -

 fr / k,

where K is the division ratio, often with the first counter 8, equal to 2 j

N, 3 is the maximum capacity of the counter 9, is equal to, m is the counter width of the counter 9.

Taking n t, we have

t - (lj ".) i ki

 f, - f; -vSo

.

+ Kjt.

In order to provide a standby mode of operation 25, the first input of the first element, AND-NO, must be connected to the output of the comparator, and the input of the driver to the external start bus.

thirty

Claims (1)

Invention Formula five 0 An adjustable pulse delay device containing the first trigger, a comparator, a resistive voltage divider connected between the device input and the common bus, and a midpoint to the first input of the comparator, a time setting RC circuit connected between the device input and the common bus, and a midpoint - to the second input of the comparator, characterized in that, in order to expand the range of adjustable delays while simultaneously increasing 5 accuracy, the first and second counters are additionally added to it, the second, third and fourth trig EASURES generator, two AND-NO element, four OR-NO element and a driver, wherein the device inlet is connected to a first input of the first AND-NO element, a second input coupled to an invariant, population-inverted output of the first flip-flop, the direct output of which is connected to the first input of the first element OR NOT, the output of which is connected to the control input of the generator, the output of which is connected to the counting input of the first counter, the first input of the second ele 11А977258 ment or NOT, the second input of the third trigger and the first input is connected to the inverse output of the second fourth element OR NOT, the second trigger, and the output is connected to the first input of which is connected to the inverse of the third element OR NOT, the second input output of the third trigger, first output connected to the output of the fourth element of the IS-NOT connected to the single element of the IPI-NOT, and the output - the sleepy input of the second trigger and the second input of the second counter, the output input of the second element of the IS-NOT, the output of which is the output which course connected to a single unit, the output of the comparator through the fourth trigger trigger, and the second world leader connected to a single input / input - to the direct output of the second trigger of the first trigger, the output of the first-hogger, the reset input of the fourth trigger counter, connected to the resetter input, and the second input of the first element of the second trigger, with a single input OR NOT.