SU1525878A1 - Pulse shaper - Google Patents

Abstract

The invention can be used in pulsed and computing. The purpose of the invention is to expand the field of application of the shaper by increasing the time interval separating the output pulses to a predetermined value. The device contains the first integrating RC - circuit (resistor 8, capacitor 9), the first trigger on the elements AND-NOT 6,7, the second trigger 11 on the elements AND-NOT 17,18, the second integrating RC - circuit (resistor 1, capacitor 2) , the third trigger 4 on the elements AND-NOT 15,16, the element AND-NOT 5, the input bus 12, the output bus 13,14. The goal is achieved by introducing an element AND-HE 5, a second integrating circuit (elements 1,2) and a third trigger 4. This allows forming on two output buses pulses separated in time between each other by a predetermined time interval. 2 Il.

Description

The invention relates to a pulse technique and can be used in devices for processing discrete information, for example, in memory devices for controlling the process of writing - reading information.

The purpose of the invention is to expand the field of application by increasing the time interval separating the output pulses to a predetermined value.

Fig. 1 shows the functional diagram of the former J in Fig. 2, the voltage plots showing the operation of the former.

The pulse shaper contains the first integrating KS-circuit (resistor 1, capacitor 2), the first trigger 3 on the elements AND-HE 4 and 5, the second trigger 6 on the elements AND-HE 7 and 8, the second integrating RC circuit (resistor 9, capacitor 10), the third trigger 11 on the elements AND-NOT 12 and 13, the element AND-NOT 14, input bus 15, output buses 16 and 17. If necessary, to accelerate the charge of capacitors 2 and 10, respectively, through resistors 1 and 9, parallel to resistors 1 and 9, diodes 18 and 19 can be connected.

The first unit input of the first trigger 3 on the AND-HE elements 4 and 5 is connected to the second unit input of the third trigger 11, the first unit input and the first zero input of the second trigger 6 and the input tripod 15, the Zero input of the trigger 3 is connected to the forward output of trigger 6 The inverse output of trigger 3 is connected to the second zero inputs of flip-flops 6 and 11. The second unit is single input of flip-flop 6 is connected to the output of the first integrating KS circuit, whose input is connected to the inverse output of flip-flop 11. The forward output of trigger 11 is connected to the first input element and- E pshne 14 and output 16. The output of AND-IE 14 is connected to a first input of a zero latch unit 11 and the second input of the flip-flop 3. To the second input of the NOR element 14 connected to the forward output. trigger 3 and the input of the second integrating KS-circuit, the output of which is connected to the first single input trigger 11 Inverse output trigger 6 is connected to the output bus 17.

The pulse shaper can be implemented on three chips 133LA4 / 155LA4 /, as diodes 18

and 19 diodes 2D503A, V / 2L509A / can be used.

In Fig. 2, the following notation is accepted: and - the voltages at the corresponding points of Fig. 1JE are the voltage

five

0

five

0

five

0

five

0

five

aor

- E ° - voltage U is the threshold of the operation of the logic element; T is the period of the following input pulses on the splint 15; t is the pulse duration on the bus 15; Court - the duration of the pulse on the output bus 16; t (j is the pulse duration on the decoder bus 17; t is the duration of the pause between pulses on buses 16 and 17.

The pulse shaper operates as follows.

In the initial state, after turning on the power source, the input bus 15 receives a high voltage level E. Capacitors 10 and 2, due to the input leakage current of the elements AND-HEN 12 and 7 of the flip-flops 11 and 6, are recharged to the level E °. On the output bus 16 and the output of the element AND-HE 7, the voltage level E is set, and on the output bus 17, the outputs of the elements AND-HE 4, 13 - the voltage level E °.

When the front edge of the input pulse appears on the bus 15, the AND-HE 4 element switches to one state, and the AND-HE 5 elements go to zero. The IS-NE 13 trigger 11 triggers and the E level appears at its output. The AND-NE element 8 switches to one state and a voltage level E appears on the output bus 17. Elements NAND 12 and 7 do not change their states.

The capacitor 10 begins to charge through the resistor 9 due to the output current of the element AND-NOT 4 from the level E to the voltage level E, and the capacitor 2 through the resistor 1 due to the output current of the element IS-NOT 13. In the case of parallel connection to the resistors 9 and 1, respectively, of diodes 19 and 18, the charge of the capacitors Yu and 2 occurs rapidly (as indicated by the dotted line in Fig. 2), which allows for a decrease in -. sew the recovery time of both KS circuits with shorter input pulses.

At the moment of the appearance of the trailing edge of the input pulse, the elements AND-NOT 12 and 7 are triggered, and at their outputs E levels appear, supporting

five

elements II-13, 8 in the closed state. On the output bus 16, the front edge of the output pulse appears. At the same time, the AND-HEY elements 14 and 5 are switched to the one state, and the AND-HE 4 element is switched to the zero state. On the output bus 17 pulse is missing. From this point in time, the process of discharge of the capacitor 10 through the resistor 9 and the output of the open element AND-HE 4 from the level E to the level E ° begins.

When the voltage across the capacitor 10 reaches the threshold level Ufjop

the IS-NO 12 element is triggered, at its output a U13 pole E appears, i.e. the leading edge of the pulse on the output bus 16 is formed. At the same time, the element NE-13 switches to zero, additionally locking the element IS-NOT 12. By quickly switching trigger 11 to its initial state when the voltage on the capacitor 10 reaches Up ™ the trailing edge of the output pulse on bus 16 is formed with a fairly steep front. The pulse duration on bus 16 is determined by the expression

and,

15

 , 0

E

Ufiop

where R- is the resistance of the resistor 9; C, about - the capacitance of the capacitor 10; E is the voltage of a logical unit;

and „„ p - voltage threshold of the logic element, appearing at the output

since

element

I-NE 13 of trigger 11 of level E begins the process of discharge of capacitor 2 through resistor 1 and the output of the open element AND-HE 13 from level E to level E. At the time the voltage across the capacitor 2 reaches the threshold

U values

pore

triggered item

NAND 7, a voltage level E appears at its output. The IS-NE element 8 is then switched to the zero state, additionally locking the AND-HE element 7.

On the output bus 17, the front edge of the output pulse appears. At the same time, the rapid switching of the trigger 6 to the initial state ensures a high steepness of the leading edge of the pulse on the bus 17.

The time interval between the end of the pulse on the bus 16 and the occurrence of 1525878

pulse bus duration

17 is determined

0

five

0

five

D

five

0

five

0

five

Where

R, - With Unop

the resistance of the resistor 1, the capacitance of the capacitor 2. The output pulse on the bus 17 ends at the time of the arrival of the next input pulse on the bus 15. Then all the processes are repeated.

The pulse duration on bus 17 is determined by the expression

g

C „„ T - t “. - (PqC.o + .C

-Ua -ex where T is the period following the input pulses;

t (is the duration of the input pulse.

Thus, on the output buses 16 and 17, output pulses with steep edges are formed, separated by a period of time, the duration of which is determined by the constant time of discharge of the first integrating RC circuit (resistor 1, capacitor 2).

The impulse on bus 16 appears at the moment of the end of the input pulse, and the impulse on bus 17 ends at the moment of occurrence of the next input impulse.

Claims (1)

The driver allows forming on two output buses pulses separated in time between each other by a predetermined (acceptable) period of time, the duration of which is determined by the constant time of discharge of the first integrating RC circuit and is chosen sufficient for reliable operation of the driver with other devices. This is due to the fact that the leading edge of the output-i pulse on bus 17 does not appear immediately after the end of the output pulse on bus 16, but only after the time when the voltage on the capacitor 2 of the first integrating RC circuit decreases to paBHovi threshold switching element AND-NOT 8 trigger 6. Invention Formula A pulse driver containing two triggers, the first one input of the first of which is connected to the first one and first zero inputs of the second trigger, the second zero input of which is connected to the output of the first trigger, the zero input of which is connected to the direct output of the second trigger, the second one the input of which is connected to the output of the first integrating RC circuit, and the inverse output to the first output bus, characterized in that, in order to extend the region of application, by increasing to a predetermined value of the gap in A separator separating the output pulses is entered into the NAND element, the second integrating RC circuit and the third trigger, the input of the first integrating RC circuit being connected to the inverse output of the third trigger, whose direct output is connected to the second output bus and the first input of the NAND element, the output of which is connected to the second single input of the first trigger and the first zero input of the third trigger, the second zero input of which is connected to the inverse output of the first trigger, the direct output of which is connected to the second input of the NAND element and the input of the second integrating RC circuit, the output of which is connected to the first single input of the third flip-flop, the second single input of which is connected to the first single input of the first flip-flop.