SU1538233A1 - Pulse generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computer automation and control devices. The purpose of the invention, the extension of the field of application, is achieved by allowing the control of the moment when the output pulses are formed without distorting them. The pulse generator contains the elements AND-NOT 1 and 2, transistors 3-6, resistors 7-12 and capacitors 13 and 14. To achieve this goal, three transistors, a second capacitor and three resistors are added to the pulse generator. In the generator, it is possible to control the time at which the output pulses form. In this case, with each control pulse, the generator switches to the initial state. 1 il.

Description

(54) PULSE GENERATOR (57) The invention relates to a pulse technique and can be used in automation, computer engineering and control devices. The purpose of the invention is the expansion of the scope of application —h is achieved by providing the ability to control the moment of formation of the output pulses without distortion. The pulse generator contains NAND elements 1 and 2, transistors 3-6, resistors 7-12, and capacitors 13 and 14. To achieve this goal, three transistors, a second capacitor, and three resistors are added to the pulse generator. The generator provides the ability to control the moment of formation of the output pulses. In this case, with each control pulse, the generator switches to the initial state. 1 ill.

1,538,233 A

The invention relates to pulsed electronics and can be used in automation, telemechanics, computing, control devices. $

The aim of the invention is to expand the scope by providing the ability to control the moment of formation of the output pulse. , θ owls without distortion,

The drawing shows a diagram of the generator.

The pulse generator contains series-connected elements Y-NOT Ί and 2, transistors 3-6, resistors 7-12 and capacitors 13 and 14. One output of the AND-NOT 1 element is connected to the device input by a resistor 12, the second terminal of which is connected to the second ₂ θ the input of the AND-NOT 2 element and capacitor 14, the base of the transistor 3 is connected to the output of the AND-NOT 1 element, the emitter is connected to the capacitor 13 and resistors 8 and 10. The second output of the resistor 25 10 is connected to the base of the transistor 4, the collector of which is connected to another the output of the capacitor 13 and the base of the transistor 5, the emitter of which is connected connected to the collector and the base of the transistor 6, and the collector to the other terminal of the AND-NOT element 1. Other outputs of the capacitor 14, the resistor 8 and the emitters of the transistors · 4 and 6 are connected to the housing bus, and the power bus through the resistors 9-11 is connected to the collectors respectively transistors 3-5, and the output of the AND-NOT 2 element is the generator output. Logical elements of microcircuits can be selected as AND-NOT elements, and transistor assemblies are advisable to use as transistors. ·

The generator operates as follows.

In the absence of control signals at the input terminal of the AND-NOT 1 element, potential 1 is maintained. When a potential 0 is generated at the other input of the AND-NOT 1 element, level 1 is formed at its output, which opens transistors 3 and 4. A fast charge of the capacitor 13 occurs with a current limited resistor 9 according to the permissible limit for transistors 3 and 4. A small collector-emitter junction voltage of transistor 4 leads to blocking of transistor 5 and opening of AND-NOT element 1. The charge of capacitor 13 stops and its discharge begins through cutting the blinds 7 and 8, wherein the transistor 5 remains closed as long as the voltage at its base is less than the threshold opening which is equal to the voltage drop across the two base-emitter junctions of transistors 5 and

6. When the transistor 5 is opened, a negative drop is formed on its collector, which closes the AND-NOT 1 element, and the process repeats. Moreover, the resistor 10 is current-limiting for the base current of the transistor 4, and the resistor 11 provides the best opening and speed elements AND NOT 1.

Upon receipt of a level 0 control signal at the generator input, the AND-NOT 1 element closes and the capacitor 13 charges as described. Since the voltage drop at the open collector - emitter junction of transistor 4 when the capacitor 13 is charged is less than the unlock threshold of transistor 5, which is equal to the unlock voltage of the base - emitter junction of transistors 5 and 6, it remains closed (or closes). So that the control pulse does not pass to the output of the device, it is delayed on the circuit by a resistor 12 - a capacitor 14 and, as a blocking one, enters the input element = that AND NOT 2.

After each arrival of the control pulse, the charge of the capacitor 13 is completely restored, regardless of the previous state. The formation of the output pulse is delayed (shifted) by the time of the discharge of the capacitor 13 from the moment of the end (cutoff) of the control pulse. The rest of the work cycle in this case is the same with the regeneration mode.

Possible variant of the device when the resistor. 7 is connected not to the power bus, but to the output of the AND-NOT 2 element (as in the known device). But this causes an increase in the instability of the generator period due to a decrease in the discharge rate of the capacitor 13 and therefore is impractical.

In known devices, the arrival of input control pulses to one or another input must strictly correspond to the state of the generator5, otherwise a pulse, pulse formation, or absence

For example, on the pulse interval, the AND-NOT 1 element is open; the AND-NOT 2 element is closed

1538233 6 the moment of formation of the th impulse of the spaced impulse to yes, i.e.

manager in the initial repent.

managing every distortion of false immanagement.

formation, ele, control of the output pulse by input 13 is impossible, since the other input of this element has a potential of 0, and by input 12 leads to shortening or distortion (cutting) of the output pulse. To prohibit its formation by the control signal, the introduction of additional synchronization circuits is required.

In the proposed generator, the control signal performs two actions: it locks the output driver on the AND-NOT 2 element and acts on the charge circuit. The generator pulse has a short duration (equal to the signal delay along the base-collector circuit of the transistor 5 plus the switching delay of the AND-NOT 1 element). Therefore, if the AND-NOT 2 element starts to switch under the action of a generator pulse, the inhibit pulse of the control signal is on. another input of its not the first output from the cutoff value, the pulse generator pulse returns the state - restart-

Claims (1)

Claim A pulse generator containing two series-connected AND-NOT elements, a timing circuit from a resistor and a capacitor connected in series, a first transistor whose collector is connected to one input of the first AND-NOT element, two resistors, distinguishing-: expanding the scope by providing the ability to control the moment of formation of the output pulses without distortion, three transistors, a second capacitor and three resistors are introduced into it, while the base of the second transistor is connected to the output of the first AND-NOT element, the collector through the second resistor connected to the bus turns off and practically does not distort the output pulse, since the pulse duration is commensurate with the switching time of the AND-NOT element. The control pulse received at any other moment of the period does not lead to interference formation of the output signal, since it is self-blocking on the NAND 2 element. A condition for high-quality blocking is the synchronism of the direct and inverse signals at the inputs of the NAND 2 element, which is achieved by selecting a resistor circuit 12 - capacitor 14. Control pulses can be received repeatedly with an interval less than the period of the generator pulses. The formation of the output pulse occurs. only in cases where the interval between control pulses exceeds the period of the generator, while 30 supply, and the emitter with the third and fourth resistors and through the capacitor of the timing circuit with the collector of the third transistor, the second output of the fourth resistor is connected to the base of the third transistor, the collector of which is connected to the base of the first transistor and through the first resistor to the power bus, the collector a first transistor via pyaD0 fifth resistor connected to the power bus, and an emitter - base and the collector of the fourth transistor, the second input of the first aND-NO element is connected through a sixth resistor to the second input of the second _{4 May} element -NOT and the second capacitor, the other terminal of which is connected to a second terminal of the third resistor, the emitters of the third and fourth transistors 50 and common bus.