SU1432732A1 - Univibrator - Google Patents

Abstract

The invention relates to a pulse technique and can be used as a high stability frequency divider. The purpose of the invention is to enhance the functionality by forming output pulses, the duration of which is a multiple of the repetition period of the input pulses, while simultaneously increasing their accuracy and stability. The single-oscillator contains a generator of 1 trigger pulses, a logical element AND-HE 3, a logical element NOT 7. Resistors 2.4 form a divider of the positive output voltage of the generator 1) and zero voltage at the output of the element AND-NOT 3. As a result, the input the AND-NE 3 logic element from generator 1 receives a voltage equal to approximately 50% of the supply voltage. Switching moments of the single & The bratra always coincide with the moments of the appearance of zero pulses from the output of the generator 1, since these pulses stimulate such switching. 2 Il. (L

Description

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The invention relates to a pulse technique and can be used as a high stability frequency divider.

The aim of the invention is to extend the functionality by forming output pulses, the duration of which is a multiple of the repetition period of the input pulses; While simultaneously increasing their accuracy and stability, FIG. 1 shows a printable one-shot circuit; in fig. 2 - diagrams of his work,

The device contains a generator 1 triggering pulses, the output of which through a resistor 2 is connected to the first input of the logic element AND-NOT 3, a resistor 4 connected by an inter- | remote control to the first input and output of the element 3 the element NOT 7, the output of which is connected to the second input of the element AND- NOT 3,

The device works as follows.

From generator 1 to the input of the IS-NE element 3, a positive voltage arrives, which periodically drops to zero, forming a pause (Fig. 2a). If the output of the HE element 7 has a single signal, then the incoming noise pulse ( at the moment t,) the occurrence of the IS-NE 3 1 unit signal appears in the code of FIG. 2c. Indeed, at the previous moment, at one input of the element AND-HE 3 there is a single signal from the output of the element HE 7, and at the other input the voltage is approximately 50% of the supply voltage, since resistors 2 and 4 form a divider of the positive output voltage generator and zero voltage at the output of the element AND-HE 3 (FIG. 26) 4 Such a stable state of the element AND-NOT 3 is disturbed by the zero signal of the generator 1, whereby at the output of the element IS-HE 3 a single signal that through a capacitor

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5 is fed to the input element HE 7, a zero signal appears at the output of KOTopoi o. This signal keeps the element HE 7 in a steady state until, due to the charge of the capacitor 5 through the resistor 6, the voltage (fig. 2g) at the input of the element drops to a level close to the triggering. One-shot switching (FIG. 2d) (time tj) occurs. In the interval between t and t at time t, the zero signal arrives at the input of the HE element 7, reducing the input signal level by 50%. However, this signal is not enough for a steady reset of the AND-NOT element 3 to the zero state, since it is held by the zero signal from the output of the element HE 7,

The switching times t always coincide with the occurrence of zero pulses from the output of generator 1, since these pulses are stimulating such switching.

Claims (1)

Invention Formula A single-oscillator containing a trigger pulse generator, the output of which is connected to the first input of an NAND logic element, whose output is connected via a capacitor to the input of a NOT logic element, and the output of the logic element is NOT connected to one of the terminals of the resistor. with the second input of the logical element IS-NOT, characterized in that, in order to melt the functionality by forming output pulses, the duration of which is a multiple of the repetition period, the input pulses, while simultaneously increasing their accuracy and stability, two additional resistors are introduced into it, one of which is connected between the output of the trigger pulse generator and the first input of the NAND gate, and the other between the same input and the output of the NAND gate, iz tj is FIG. 2