SU1621142A1 - One-shot multivibrator - Google Patents

Abstract

The invention relates to a pulse technique. The purpose is to increase the stability of the output pulse duration and expand the range of use by increasing the range of allowable start-up pulse durations by introducing logic element 2 OR 9 and logic element 2 AND 8, transistors 13 and 14 of various types of conductivity and resistors into the waiting multivibrator. 10-12. The standby multivibrator also contains logic elements 2I-NOT 1,2, forming an RS flip-flop, resistor 3, time giving capacitor 4. Resistors 3, 10-12 and transistors 13, 14 form two controlled current generators. 2 Il.

Description

The invention relates to a pulse technique and may find application in the development of electronic devices.

The aim of the invention is to increase the stability of the duration of the output pulse and expand the scope of the standby multivibrator by increasing the range of allowable durations of the start pulse.

Figure 1 presents the electrical circuit of the waiting multivibrator: figure 2 is a timing diagram of its operation.

The standby multivibrator contains the first and second logical elements 2I-NOT 1 and 2, forming an RS-flip-flop, the first resistor 3, a timing capacitor 4, a control bus 5, a start bus 6, an output bus 7, a logic element 2I 8, a logic element 2 OR 9 the second is the fourth resistors 10-12, the first 13 and second 14 transistors, and four resistors and the first and second transistors form two controlled current generators.

The standby multivibrator works as follows.

In the initial state, on the bus 6 there is 1, on the bus 7 1, at the direct output of the trigger and at the output of the logic element 2I 8 0, the capacitor is fully charged (see Fig. 2c). When the zero trigger pulse arrives on bus 6, the trigger is reset to a single state, a low level signal appears on bus 7, logic elements 8 and 9 open to pass the control signal from bus 5 to the bases of transistors 13 and 14 (see Fig. 2a, b) . If a single signal is present on bus 5, then the transistor 13 is closed, and the transistor 14 together with resistors 10 and 12 forms a current generator, which charges the capacitor 4 according to a linear law (see Fig.2b, c). By applying a series of pulses to the bus 5, we get a sequence of discharges and charges of the capacitor 4. By changing the duty cycle of the pulse sequence on the bus 5, you can adjust the discharge speed of the capacitor 4. At the moment when the voltage across the capacitor reaches the zero threshold of element 214 - ΉΕ 2, the output of element 2 and a single signal appears on the output bus 7 (see Fig. 2e), the formation of the output pulse ends. At the output of element 2 OR 9, a high level signal appears, and if a low level trigger signal is present on bus 6, a high level signal is present at the output of element 8 and capacitor 4 continues to discharge through transistor 14. When a high level signal appears on the trigger bus 6 the output of element 8, a zero signal appears and the capacitor 4 begins to charge through the transistor 13 to a maximum value.

The use of this invention in comparison with known devices provides increased stability of the formation of the duration of the output pulse and the expansion of the functionality of the device by increasing the range of allowable durations of the start pulse.

Claims (1)

Claim A waiting multivibrator containing an RS-flip-flop, the S-input of which is connected to the trigger bus, and the R-input through a timing capacitor is connected to the common bus, the inverse output of the RS-flip-flop is connected to the output bus, the first resistor, the control bus, characterized in that, in order to increase the stability of the duration of the output pulse and expand the scope by increasing the range of allowable durations of the start-up pulse, the logic elements 2IL14 and 2I, two transistors of different conductivity types and three resistors are introduced into it, one of the inputs of the 2OR logic element is connected to the control bus, the other input is an inverse output of the RS-flip-flop, the direct output of which is connected to one of the inputs of the 2I logic element, the other input of which is connected to the output of the 2OR logic element, and the output, respectively, through the first and second resistors with the bases of the first and the second transistor, respectively, the collectors of the transistors are connected to the R input of the RS-flip-flop, the emitter of the first transistor is connected to the bus of the power source, and the emitter of the second is connected to the common bus, the base of the first transistor is connected on the bus power source via a third resistor. and the base of the second - with a common bus through the fourth resistor. FIG. 2