SU1492456A2 - Variable frequency pulse generator - Google Patents

Abstract

The invention relates to a pulse technique, is an improvement of the device according to the author. N 1267593 and is intended to expand the functionality of the device by ensuring a smooth adjustment of its output frequency in any direction. The purpose of the invention is achieved by introducing into the device an inverter 8, a subtracting pulse counter 9, a second block 10 of feedback functions, a switch 11 and new functional connections. In addition, the device contains a pulse generator 1, a sum pulse counter 2, a controlled frequency divider 3, a first block 4 of feedback functions and a discrete delay element 5. Depending on the direction of the frequency change, the summing 2 or subtracting 9 pulse counter operates. The output frequency is determined by the division ratio of the controlled frequency divider 3, the input of which receives the output code of the summing counter 2 pulses. The inclusion in the circuit of the counting input of one of the counters 2 (9) of the pulses, the frequency divider 13 provides a different rate of change in frequency depending on its direction. 13.pf-ly, 1 ill.

Description

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The invention relates to a pulse technique, can be used in the control equipment of static converters, as well as to create frequency-controlled pulse generators and is an improvement of the invention according to the author. No. 1267593.

The aim of the invention is to extend the functionality of a pulse generator with a controlled frequency due to the smooth tuning of the output frequency in any direction

The drawing shows a functional diagram of a variant of an impeller with a controlled frequency.

The device contains a pulse generator 1, a summing pulse counter 2, a controlled frequency divider 3, a first block 4 feedback functions, a discrete delay element 5, a first control bus 6, an input I bus 7, an inverter 8 /

Pogo is connected to the counting input of a summing counter of 2 pulses and through a frequency divider 13 to the counting output of a counting counter of 9 pulses. The output of the divider 3 purity connected to the input of the element 5 discrete delay and to the output bus 14 of the device.

Blocks 4 and 10 of the feedback functions can be performed on AND elements, the number of inputs of which correspond to the number of units in the codes decoded by them.

The device works as follows.

The control bus 12 receives a signal with a logic level corresponding to the switching at the outputs of the switch 11 signals from its second group of inputs. In the initial state, the device operates in the nominal frequency mode, in which the summing counter of 2 pulses

 A subtracting counter of 9 pulses is automatized with a signal arriving at its

A second feedback function block 10, a switch 11, a second control bus 12, a frequency divider 13 and an output bus 14.

Input information bus 7 under the Function of block 4. The same number

It is connected to the first group of inputs of the switch 11, the second rpyinia whose inputs are connected to the outputs of the subtracting counter 9 pulses. The second control bus 12 is connected to the control input of the switch 11, the outputs of which are connected to the information inputs of the summing counter 2 pulses, the outputs of which are connected to the information inputs of the reading counter 9 pulses, to the information inputs of the controlled splitter 3 frequencies and to the inputs of the first block of 4 functions feedback, the output of which is connected to the prohibition input of the summing counter 2 pulses, the recording input of which is connected to the first control pad 6 and to the input of the inverter 8, the output of which is connected to the input in the subtraction counter record 9

pulses, the prohibition input of which is connected to the output of the second block 10 of feedback functions, the inputs of which are connected to the outputs of the subtracting counter 9 pulses.

The pulse generator 1 is connected to the counting input of the controlled frequency divider and the synchronous input of the discrete delay element 5, the output from

input from the output of the block 4 feedback functions. At the outputs of this counter there is a binary number, the value of which is determined by the selected

is present at the outputs of the subtracting counter 9 pulses, since the information inputs of this pulse counter are connected to the outputs of the totalizing counter 2 pulses, and at the recording input of the subtracting counter 9 pulses a re-write enable signal is generated. The pulses from the output of the pulse generator 1 are fed to the counting input of the controlled frequency divider 3 and the synchronous input of the discrete delay element 5. The control divider frequency 3 has a division factor defined by a binary number formed at the outputs of the summing counter 2 pulses. As a result, a pulse train whose frequency is equal to f will be formed on the output bus 14 of the device.

In the mode of switching to another frequency on the control bus 6, the signal changes the logical level and is fed to the input of the record of the summing counter 2 pulses and after inversion to the input of the subtracting counter 9 pulses. As a result, the work of the subtracting counter of 9 pulses becomes possible, since at its

51492456

During the prohibition, the prohibiting signal of otna and knowledge of obs and then those

is absent (it is assumed that the numbers at which blocks 4 and 10 of the feedback functions form signals that prohibit counting are different), and the counting input of the subtracting counter 9 pulses from the output of the controlled divider 3 frequencies through the discrete delay element 5 receives pulses from the output bus 14 device. As a result, the number at the outputs of the subtractive counter 9 pulses begins to decrease as each clock pulse arrives. The code of this number through the switch 11 is fed to the information inputs of the summing counter 2 pulses, which operates in the mode of parallel rewriting from their inputs.

In this case, the frequency at the output of the device begins to gradually increase. This process of increase in frequency continues until

the output of block 10 of the feedback value of the initial value - 25 at the removal of this is not generated a logical signal, which is fed to the input of the prohibition of the subtracting counter 9 pulses. As a result, a no30 is installed on the output bus 14 of the device.

th signal.

Claims (2)

The positive effect of the proposed device in comparison with the known one is to provide the possibility of a smooth change to either side of the output frequency of the device and to provide a different rate of change of frequency depending on the direction of this change. Formula invented and the new value of the frequency f determined by the selected feedback function block 10. This new value of the output frequency is maintained until i iiop until the logic signal changes on control bus 6. After changing this signal, the reverse frequency transition of the output frequency to its initial value f begins. In the mode of reverse transition to the nominal frequency, the summing counter 2 pulses starts to operate in the counting mode, and the subtracting counter 9 pulses - in the mode of rewriting information from its information inputs, information on which comes from the corresponding outputs of the summing counter 2 pulses. In this case, the frequency on the output bus 14 of the device begins to gradually decrease. This graphic process lasts until a logical signal is generated at the output of the block 4 of the feedback functions, which is input to the prohibition input of the summing counter 2 pulses. As a result, the initial value of the output frequency fj is set on the device output bus 14. 0 The duration of the transition to the new value of the output frequency and the reverse transition to the nominal value of the output frequency are determined by the numbers at which feedback blocks 4 and 10 prohibit the operation of counters 2 and 9 pulses, respectively, and the output period of the pulse generator 1. In addition, the duration of the transition to the frequency fj depends on the magnitude of the division factor of the frequency divider 13. When a signal arrives at control 5 of board 12 with a logic level corresponding to switching signals from the first group of inputs to the outputs of switch 11, the device operates in the same way as the known one. At the same time, when the recording of the summing counter 2 pulses of the recording signal is applied to the recording input, an abrupt change in the output frequency of the device occurs, followed by a smooth change to the first initial value when removing this th signal. The positive effect of the proposed device in comparison with the known one is to provide the possibility of a smooth change to either side of the output frequency of the device and to provide a different rate of change of frequency depending on the direction of this change. Formula invented and 1, Pulse generator with controlled frequency according to auth.St. No. 1267593, - characterized in that, in order to expand the functionality due to the smooth tuning of the output frequency in any direction, a subtracting pulse counter, a second block of feedback functions, an inverter, a switch and a second control bus connected to the control input of the switch, the first group of inputs of which is connected to the input information bus, the first control bus is connected to the input of the inverter, the output of which is connected to the recording input of the subtractive pulse counter, whose outputs are connected to the second group of inputs of the switch and in parallel to the inputs of the second block of feedback functions, the output of which is connected to the prohibition input of the subtractive pulse counter, 714924568 formation inputs of which 2. Generator but p. 1, about 1 and - to the outputs of the summing counter, in that the output of the pulses, the information inputs of the discrete delay terminal are connected to the outputs of the commutator with the counting input of the summing or pa, the counting input of the subtracting A counter-subtracting pulse counter through k pulses is connected to the output of an ele- mentally introduced discrete-time delay divider.