SU1488822A2 - Unit controlling data transmission in multiprocessor system - Google Patents

Description

The invention relates to computing and is intended for decentralized control of the transfer of information between components of a computer system. The purpose of the invention is the extension of functionality due to the implementation of the mode of random polling. Mouth

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The device contains transmitter 1, receiver 2, buses 3-5, output signal generator 6, first trigger 7, key 8, bus 9, pulse generator 10, frequency divider 11, elements AND 12, 13, input adapter 14, element OR NOT 15, element OR GB, start block 17, shift register 18, element OR 19, element 20, counter 21, decoder 22, interval continuation completion block 23, counter 24, decoder 25, counters 26, 27, blocks of elements And 28 , 29, comparison block 30, trigger 31, pseudo-random sequence generator 32, OR element 33, subscriber number register 34, AND 35, 36, b blocks of elements approx 37 comparisons, the delay element 38, flip-flop 39, AND gate 40, the switching unit 41. 1 il.

The invention relates to computing, is intended for decentralized control of the transfer of information between components of computer systems and is 20

improvement of the device on the main auth. St. No. 1336024,

The purpose of the invention is the extension of functionality due to the implementation of the mode of random polling, 25

The drawing is a diagram of the device.

The device contains a transmitter 1, receiver 2, output bus 3, input bus 4, common bus 5, signal generator 6, first trigger 7, key 8, information bus 9, generator ¹ 10 pulses, divider 11, second and third elements AND 12 and 13, input adapter 14, element OR-NOT 15 pause, first element'IL or 16, block 17 start- $$ start, shift register 18, second element OR 19, first element I 20, first counter 21, decoder 22, block 23 completion / continuation of the interval, the second counter 24, the second dd decoder 25, the third and quarters counters 26 and 27, the first and second blocks 28 and 29-element And, the first comparison block 30, the second trigger 31, the pseudo-random sequence generator 32, the third element OR 33, the subscriber number register 34, the third; the fourth blocks 35 and 36 And elements, the second comparison block 37, the 'delay element 38 , the third trigger 39, the fourth element And 40, the switching unit 41.

The device works as follows.

All devices connected to the $$ common bus 5 are assigned a number in a cyclic order. In accordance with the number of devices, as well as taking into account their priorities, the length is selected.

time intervals, and specific installation inputs for the distributor of each device are determined. Thus, each device, taking into account the priority, is allocated one or several time intervals for transmitting information, the length of which may vary depending on the presence or absence of information from this source for transmission to a common bus.

The device has two modes of operation - the cyclic polling mode and the random polling mode. The first mode is used when a high intensity of information is received from information sources, and the second mode is used at a low intensity. Switching modes of operation occurs automatically using block 30, trigger 31 and switching unit 41, which are connected to the second input of the element 20 or the output of register 18 in the cyclic polling mode, or the output of the trigger 39 in the random polling mode. The random polling mode corresponds to the single state of the trigger 31. The cyclic polling mode corresponds to the zero state of the trigger 31. The intensity of information receipt from sources is analyzed using the counter 24, the second decoder 25, the third Counter 26, the fourth counter 27, blocks 28 and 29 elements And, block 30 comparison, trigger 31 and delay element 38. The analysis is carried out for a cycle of polling all devices, equal to the total specific number of intervals in the system.

Random survey carried out with

using a 32-pseudo-random sequence generator; element

OR 33, register 34 subscriber numbers,

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blocks 35 and 36, block 3.7 comparison, trigger 39, element And 40. The survey occurs when a pulse appears on one of the inputs of the element OR 33, which is compared in block 37 comparing the contents of the generator 32 pseudo-random sequence and the subscriber number register 34, which binary codes on the corresponding outputs of the generator 32 of a pseudo-random sequence and the register 34 of the subscriber number match, the signal from the output of the comparison block 37 translates into a single 15 state trigger 39 and it gains control over the common bus 5, with the proviso that the flip-flop 31 is in set condition.

Such a management organization 20 of the transfer process allows for cyclical polling to provide the ability to transfer information to each subscriber with mandatory polling of all, which eliminates long downtime of more low-priority subscribers, and in case of a random polling, reduces the downtime of the common bus. The proposed device, as well as the known, is intended to control only the transfer of information. Reception of the same information and selection of recipients of a multiprocessor system should be carried out by other devices.

At the beginning of the multiprocessor system, the initial initialization of the pseudo-random sequence generators is performed for all devices of the system and different numbers are set for different autos-49 cents, and then from the leading source of information, the start signal is sent through the second input group of the receiver 2 to the first input of the unit 17 launch. Suppose that the system began to operate in a cyclical polling of subscribers. The adapter 14, permanently connected to the common bus 5, provides information about the state of the common bus 5 to the inputs of the element OR 16. If the common bus is free, the output potential of the OR 16 element is zero potential, which is allowed to be received by the start-up trigger 17, and by which - 55 a single pulse from the sequence from the first output of the divider 11, which continuously receives pulses generated by the generator 10. The capacitance of the divider 11 is selected from the condition of the full length of the transmission interval by one device.

This impulse in each of the devices sets the units to the given bits of register 18 and simultaneously sets the potential at the second output of the starting block 17, which opens the element 12 and element 40 and prepares the element 13 for the opening. When installing the valves at the device with the highest priority in the last digit, a unit is set, which through the switching unit 41 is given permission to the source of information to begin transmitting information 'and at the same time the element 20 opens, through which the input 21 of the counter pulses from the generator 10 output arrive. A 32 pseudo-random sequence generator also begins operation. At the first output of the first decoder 22 connected to the outputs of the first counter 21, a signal appears allowing the flow of information to the first group 9 of inputs of transmitter 1 through the output generator 6 of signals and the first group of outputs of transmitter 1 to the common bus 5. The input stage continuously outputs information about the state of the common bus 5 to the inputs of the element YLI-NOT 15. If the source has no information, then a pause in the common bus 5 is detected by the element OR-NOT 15, issuing permission to the end 23 / completion of the interval for wrapping the transmission interval of this device. The first counter 21 counts the second pulse coming from the output of the generator 10 through the element AND 20, a signal appears at the second output of the first decoder 22, with which block 23 starts to generate at its second output a pulse, the arrival of which at the first input of key 8 coincides with impulse from the third output of the first decoder 22, the impulse from the output of the key 8 resets the first counter 21 and the divider 11 in the device that controlled the transmission process in this interval, Thus, the termination of this int occurs tearing in the absence of information to be transmitted.

In all devices, including the one that managed the process

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and all the others, through the open element I 13, from the second output of the divider 11, arrive through the element OR 19 to the input of the shift of the register 18 a sequence pulse shifted relative to the sequence at the first output. This impulse shifts the contents of register 18 in all devices. For the device that previously controlled the transfer, the unit is rewritten to the first digit, for the next device it appears in the last digit (if the previous one had no units in two digits in a row). Managing the transfer of information to the common bus 5 is transferred to the next device, and so on.

In the case when the source has information for transmission and sends it to the common bus 5, the zero signal from the output of the OR-NOT 15 pause element is fed to the first input of the interval completion / continuation unit 23. When the pulse arrives at 25 from the second output of the first decoder 22 to the second input of the block 23, a signal appears at the first output of the block 23, which is installed in the first counter 21 30

a code exceeding, for example, a unit that corresponds to the appearance of a signal at the third output of the first decoder 22. Thus, in the first counter 21, after the code corresponding to the appearance of the signal at the second output of the first decoder 22, the code corresponding to the appearance of the signal at the fourth or subsequent outputs of the first 40 decoder 22. The capacity of the first counter 21 and the width of the first decoder 22 are selected in each particular implementation case from the provision condition for the transmission interval of the required 45 amount of information from one source. Therefore, between combinations of binary code corresponding to the appearance of signals at the third and last outputs of the first decoder 22, there may be several intermediate combinations that are not necessary to use for the operation of this device, and therefore, when implementing the scheme of the first $$ decoder 22, those combinational nodes, which serve to interpret such intermediate combinations. So the last

the output in the first decoder 22 may be fourth or more, depending on the required length of the transmission interval.

So, after the first counter 21 slip, which corresponds to the end of the interval of this device in the absence of its source information for transmission to the common bus 5, the interval continues, information from the source is transmitted to the common bus. With the advent of the signal at the last output of the decoder 22, the trigger 7 is reset, the output generator of 6 signals is closed. The first counter 21 receives at its input another impulse passing from the output of the generator 10 through the element 20 and transferring the counter to the initial zero state. Then, with some delay, a pulse appears at the output of the divider 11, passing through the open element AND 12 and the element OR 19 at the input of the register 18 shift. The appearance of the pulse at the first input of the divider 11 and the shift of the register 18 occurs in all devices of the system (working and not working in the preceding interval). The unit is set in the last discharge of the next device and the next pulse from the output of the generator 10 begins the transmission of information from its source to the common bus and so on.

During the entire survey cycle, information about the number of polled devices is accumulated in the second counter 24, information about the number of devices that did not transmit information is accumulated in the third counter 26, and information about the number of devices transmitting information in this system operation cycle is accumulated in the fourth counter 27. After the end of the transmission interval of the last device in the cycle, the pulse from the output of the element OR 19 is fed to the input of the second counter 24 and the control inputs of blocks 35 and 36. At this moment, a pulse appears at the output of the second decoder 25, which opens the blocks 28 and 29, through which the first and the second group of inputs of block 30 receives signals from the outputs of the third counter 26 and the fourth counter 27. In block 30, the contents of the third and even pairs are compared

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true counters. If the contents of the third counter 26 are greater than the contents of the fourth counter 27, then a high level signal appears at the output "More" of block 30 (if $ is vice versa, then a high level signal appears at the output "Less than or equal to" block 30), translating the trigger 31 into the unit state, the unit from the direct output of the trigger 31 enters the control input of the switching unit 41 and connects the output of the trigger 39 instead of the output of the register 18 to the second input of the element AND 20. All devices of the system switch to the mode of random polling of subscribers. At the same time through the open blocks 35 and 36 to the inputs of the block 37 comparison are read. codes from the generator outputs 32 pseudo-20 random sequence- and register 34 of the subscriber number. After that, the signal from the output of the second decoder 25 through the delay element 38 resets the third and fourth counters 25 26 and 27. If the codes from the generator 32 and register 34 do not match for one of the subscribers, then at intervals (long if the previous one in the cycle was short, or short if the last previous one was long) these codes will be read again, etc. If any device of the system coincides, then at this device, at the output of comparison block 37, a signal appears that takes the trigger 39 into a single state. The unit from the output of the trigger 39 of the proposed device enters through the switching unit 41 to the second input of the element I 20 and opens it. The pulses from the generator 10 through the element And 20 begin to arrive at the input of the first counter 21 and the further operation of the device is similar to the work in the cyclic polling mode. After the end of the transmission interval of the selected device, a pulse comes either from the output of the key 8 (no information) or from the last $ output of the first decoder '22 (was information) to the second input of the OR 33 element. This pulse resets the trigger 39 and prepares for the selection of the next device . After the survey cycle ,. equal to the number of intervals in the cycle, the intensity analysis is again performed and the system continues to operate in

according to the mode of operation selected in this analysis, etc.

Thus, at high intensity of receipt of information from sources, the device operates in a cyclic polling mode and allows you to guarantee the transfer of information from all sources to a common bus for one cycle. At the same time, if the source has no information for transmission, a smaller time interval is allocated for its maintenance as compared with the time interval allocated for servicing sources that have information for transmission. By reducing the intensity of information receipt from sources, the device operates in the mode of random polling and improves the efficiency of using a shared bus, as it reduces its downtime.

Claims (1)

Claim The control unit of information transfer in a multiprocessor system according to aut. St. No. 1336024, of which it is, in order to expand its functionality through the implementation of the random polling mode, it introduced the second, third and fourth counters, the second decoder, the four AND blocks, the two comparison blocks, the register subscriber numbers, second and third triggers, switching unit, delay element, third OR element, fourth AND element and pseudo-random sequence generator, with the output of the second OR element connected to the counting input of the second counter, the outputs of which are connected to the inputs of the second the encoder, the output of which is connected to the control inputs of the first and second blocks of the elements And through the delay element connected to the reset inputs of the third and fourth counters, the output of the second element And connected to the counting input of the fourth counter, the outputs of which are connected to the information inputs of the second block of elements And outputs which is connected to the inputs of the first group of the first comparison unit, the output of the sign "More" which is connected to the installation input in "1" of the second trigger, the forward and inverse outputs of which are connected to the control vhoda1-governing] 1488822 12 mi switching unit ^- , the output of which is connected to the second input of the first element And the output resolution of the transmission device, the output of the third element And is connected to the counting input of the third counter, the outputs of which are connected to the information inputs of the first block of elements And, the outputs of which are connected to the inputs of the second, 0 groups of the first comparison unit, the output of the sign "Less than or equal to" which is connected to the installation input to the "0" of the second trigger, the output of the second element OR is connected to the control inputs of the third and fourth blocks of elements And, the inputs of the initial installation of the device are connected to the inputs of the initial installation of a pseudo-random sequence-20 generator, the outputs of which are connected to the information inputs of the third block of elements I, the outputs of which are connected to the inputs of the first group of the second comparison block, the output of which is connected to the installation input in "1" of the third trigger, the output of which is connected to the first information input of the switching unit, the second information input of which is connected to the output; one of the shift register, the installation inputs of the subscriber's device number are connected to the setup inputs of the subscriber number register, the outputs of which are connected to the information inputs of the fourth block of I elements, the outputs of which are connected to the inputs of the second group of the second comparison unit, the output of the first And element the OR element, the output of which is connected to the 'setup input to' 0 'of the second trigger, and the second input is connected to the high-order output of the first decoder, the output of the pulse generator is connected to the first input ohm of the fourth element ₍ And, the output of which is connected to the input of the sync pulses of the pseudo-random sequence generator, the second output of the launcher is connected to the second input of the fourth element I. ,