SU1485263A1 - Queueing system simulator - Google Patents

Description

The invention relates to specialized means of computing tech2

nicks and can be used in the study of queuing systems with a heterogeneous flow of applications. The purpose of the invention is the extension of functionality due to the simulation of queues. By introducing a multiplexer, a trigger, an AND block and a queuing block, the device allows you to simulate the process of multi-instrument servicing of a heterogeneous flow of requests with a queue. At the same time, statistical characteristics are generated that most adequately correspond to real complex systems and allow synthesizing new systems that have the best performance indicators. 4 il.

The invention relates to computing, in particular to specialized electronic modeling tools, and can be used in the study of multi-instrumental queuing systems with a heterogeneous input stream of applications.

The aim of the invention is to expand the functionality of the device by simulating the process of multi-instrument maintenance of a heterogeneous flow of applications with the queue.

FIG. 1 shows a functional diagram of a device for simulating queuing systems; in fig. 2 - diagram of the control unit; in fig. 3 is a functional block diagram of a characteristic determination unit for analyzing the result of an operation in the subtraction unit and generating the corresponding control signals; in fig. 4 is a functional diagram of a queuing unit that is intended to store information about applications in the queue.

The device contains a block 1 job code, the first encoder 2, the first register 3 codes, a block of elements NOT 4, block 5 subtraction, register 6 free devices, the first multiplexer 7, block 8 of random pulse generators, the second multiplexer 9, the first element OR 10, register 11 applications, a characteristic determining unit 12, a second element OR 13, a queuing unit 14, a trigger 15, a control unit 16, a prohibition block 17, a block 18 random delays rotations, a third element OR 19, a total number of applications 20, 20, and 21 the first 22 block of elements And, the second encoder 23, second register 24 codes, adder 25, counter 26 unserved applications.

The control unit contains the first differentiating element 27, the first trigger 28, the first element And 29, the third trigger 30, the second differentiating element 31, the second trigger 32, the second element And 33.

The characteristic definition block contains the first element AND 34, the first element NOT 35,

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the third 36 and the second 37 elements are AND, the second element is NOT 38, the fourth element is AND 39, the element is OR 40, the third element is NOT 41.

The queuing unit contains the first element AND 42, the element OR 43, the element 5 delay 44, the second element AND 45, the group of elements AND 46, the group of elements OR 47, the group of multiplexers 48, the group of registers 49 of codes, the group of blocks 50 of the delay elements, the first element is NOT 51, the third element is AND 52, the second element is NOT 53, the fourth element is And 54, the second element is 55 delay, the register 56 of the order queue, the fifth element is And 57.

The block 1 of the task of the code is intended for the initial installation of the (n — 1) -bit binary code of the number of servicing devices in the register of 6 free devices.

The encoders 2 and 23 are combinational circuits that convert the posi- tion code to a normal (n - 1) -bit binary code.

Registers 3 and 24 are intended for the temporary storage of the current (n— 1) -bit binary code.

Block 5 subtraction implements the operation of subtraction by summing the code of the free number of devices, which comes from the outputs of the registers 6 free devices and the reverse binary code of the number of requested devices, which through the block 4 elements does NOT come from the first 3 register code.

OTC 04 = 15LES

thirty

[κ + ΐ] Λ0; RESET = (Otka15kh (ZPRRL15) U (15LES _ge [1]),

where OTK, ZPR are the corresponding signals that go to the output of the characteristic definition unit 12; 15, 15 are respectively the signals on the direct and inverse output of the trigger 15; /? Szb [/] - the signal at the / -th output of the register 56 queue of applications;

K - the maximum length of the queue.

Register 56 queue applications serves as a marker, ie, indicates the place in the queue, which should be recorded information about the application, which received a denial of service. The number of registry outlets is 56 per unit more than the number of places in the queue, i.e., equal to (A + 1). The presence of “1” at the (K + 1) th output indicates that the entire queue is full.

Registers 49 are designed to store application codes. 50

The request code, which is in the first queue, is stored in the first register of group 49, the second in the second register, etc., and the Kth in the Kth register. If the first of the queued applications (an application that is in the register 49ι) goes to 55 servicing, then the information about the application that is in the register 49g is copied to the register 49ι, and so on.

Register 6 of free devices is designed to store the binary code of the number of free from service devices.

The multiplexer 7 is designed to connect the information outputs of the subtraction unit 5 and the adder 25 to the bit inputs of the register of free devices 6. The following logic functions are implemented at the output of the characteristic definition unit:

Rec = Bl 5 [p]; ___

OTC = Bl5 [p] A (D B l 5 [/];

OBN = λ. Bl 5G /];

CRA = OBUZAP;

where Bl 5 [/] is the value of the / th digit of the block 5 subtraction;

ZAP - control signal "Record";

OTK - “Failure” control signal;

OBN - control signal "Zeroing";

ZPR - control signal "Ban".

Register 11 applications is intended for temporary storage of the position code of the application.

The queuing unit 14 (FIG. 4) 25 is intended for storing codes of applications that were not served due to a shortage of devices at the time of receipt of these applications, as well as for issuing the following control signals: refusal of a request for a place in the queue (QC OCH) a) due to the limited length of the queue; reset trigger 15 (RESET), which are defined as follows:

The trigger 15 of the device issues a sign that the information from the queuing unit is being read.

The device multiplexer 9 is designed to connect the outputs of the random pulse generator unit and the register 4 outputs to the digit inputs of the register 11 applications, as well as to the inputs of the first encoder 2 and the OR 10 element.

Vertical model of the device is as follows. The device initially sets the total number of service devices N of the simulated QS.

The application of the corresponding type, received at the entrance of the QS, is matched with the number of instruments t required for its maintenance. The numbers N and t are compared: if the difference (Ν — t) is greater than or equal to zero, that is, the number of devices free from servicing is greater than or equal to the number of devices requested by the application, then the application is served. At the end of the service of an application of the corresponding type, the number m of freed devices is added to the number of devices free from servicing.

If the number of service-free devices is less than the number requested for 1485263

turnout devices, the application is trying to be in the queue. The application will be placed in the queue if the number of applications in the queue is less than the maximum length of the queue K. If the entire queue is already full, the application will be rejected.

The total number of applications of each type and the number of unserved applications of each type are counted by appropriate counters.

The main modes of operation of the device.

Before starting the device, all counters, registers and triggers are reset.

Using block 1, the binary code / V of the total number of service devices is set.

Operation mode

The trigger 15 is reset, while the pulses from the generator 8 random pulses through multiplexer 9 are sent to the encoder 2, which converts the position code of the pulse (application) into (n - 1) -bit binary code of the number of devices requested by the application, which is written in register 3. Except In addition, the generator 8 pulses arrive at the element OR 10, from the output of which the pulse of writing the position code of the application enters the register of 11 applications and the register 3 of the code of the number of instruments requested by the application. The write pulse from the element OR 10 also enters the input of the control unit 16, switching the trigger 28 (FIG. 2) to one state, while if the trigger 32 is in the zero state, the trigger 30 will switch to the one state. If the trigger 32 is in the single state, then waiting occurs when the trigger 32 is reset to the zero state. The signal from the direct output of the trigger 30 connects the information output of the subtraction unit 5 through multiplexer 7 to the information input of the register 6 of free devices and enables the subtraction unit to operate, while the adder 25 cannot be initiated.

In block 5 of the subtraction, the addition of a direct binary code of the number of service devices with inverse binary codes of the number of devices requested by the application is realized. After completion of the subtraction operation in subtraction unit 5, a pulse is generated, which from the output of unit 5 enters the characteristic determining unit 12 and the control unit 16, in which, by cut of the trigger pulse 28, switches to the zero state, enabling the operation of the adder 25. The characteristic determining unit 12 analyzes the result operations in block 5 and the pulse from the output of block 5 generates the corresponding control signal. If the result of the operation is zero, i.e., in all digits of unit 5, unit 12 resets the register 6 free devices and opens unit 17

elements of the prohibition, allowing the maintenance of the application of this type, while the impulse (application) at the output of block 17 excites the corresponding input of the block 18 random time delays. If the result of the operation is greater than zero, i.e., in the sign bit of block 5 subtraction zero, block 12, the characteristic definition opens the block 17 prohibition elements, allowing servicing of requests of this type, and through the element OR 13 it excites the input of the register 6 free devices, recording in it through multiplexer 7 the result of the operation.

If the result of the operation in subtraction unit 5 is less than zero, then unit 12 generates the “Failure” signal, which is fed to the input of the queue forming unit 14 (the combined second inputs of elements And 45, 54 and 57 and the second inputs of all elements And 46 (Fig. 4) ). If the queue is not yet filled (the one output is the / th output of register 56 of the request queue, where / θ [1, K], then at the output of the / th element And 46 a pulse appears, which through the OR 47 element of the same name enters the resolution input records of the register of the application code registers of the same name, with the position code of the application from the application register 11 being entered into the selected register from group 49 through multiplexer 48. If the queue is full (in one state (/ (+ 1) -th output of register 56 '(FIG. -4)), then the application receives a refusal, i.e., a queuing generation unit 14 is generated Vaeth failure signal application providing a place in the queue, which opens the AND unit 22, impulses from the register 11 requests pass through the AND gates 22, simulating the flow of requests, receiving a denial of service. The number of such requests counter 26 is read.

Pulses from block 18, appearing on one of its outputs after a time of a random duration of service of applications of the corresponding type, arrive at the encoder 23, which converts the positional code of the pulse into a binary code of the number of devices serving the application of the corresponding type, which is recorded in register 24 of the code. In addition, the pulses from block 18 arrive at the element OR 19, from the output of which a pulse is written to write the binary code of the number of devices servicing the application. The write pulse from the element OR 19 is also fed to the input of the control unit 13, switching the trigger 32 (FIG. 2) to one state, while if the trigger 28 is in the zero state, then the trigger 30 switches to the one state. If the trigger 28 is in the single state, then waiting occurs when the trigger 28 is reset to the zero state. In the adder 25 is the addition in the direct code of the binary number of free devices with binary number t

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devices serving the application of the appropriate type. After completion of the summation operation, the output pulses (output of the summation end) of the adder 25 through the element OR 13 arrive at the synchronous input of the register 6 of free devices, recording the result of the operation of the adder 25 into the register 6 of free devices. At the same time, the pulse from the same output of the adder 25 is fed to the single input of the trigger 15 and sets it to the single state, as well as to the input of the control unit 16, where the trigger 32 switches to the zero state by cutting the pulse, allowing the operation of the subtraction unit 5.

If there is at least one request in the queue, then the trigger set in unit 15 connects the output of the first register 49 through the first block of delay elements 50 (Fig. 4), multiplexer 9 to the digit inputs of the register of 11 applications, the OR 10 element and the encoder 2 of the code and is overwritten information about the application in line. In this state, the counter 20 does not change, since AND is the logic zero level at the control input of the block of elements. After performing the subtraction operation in the subtraction unit 5, the characteristic determining unit 12 analyzes the result. If the result of the subtraction operation is less than zero, then at the output of the AND 36 element (Fig. 3) of the characteristic determining unit 12, an OTK control signal is generated, which is fed to the inputs of the And 45, 54, 57 elements and to the combined inputs of all And 46 elements, since direct output trigger 15 unit, then the unit will appear only at the output of the element And 45. This unit through the element OR 43 and the delay element 44 will arrive at the zero input of the trigger 15 and switch it to the zero state, then to the inputs of the encoder 2, the element OR 10 and register 11 applications through multiplexer 9 will connected to the outputs of the block 8 of the random pulse generator.

If the result of the operation in block 5 subtraction is greater than or equal to zero, then the application is accepted for service just as in the case of its arrival from block 8 of the random pulse generator. The difference lies in the fact that the signal from the output of the element HE 41 of the characteristic determining unit 12 is supplied through the element HE 51 to the input of the element AND 52 of the unit 14 for forming the queue (FIG. 4). Since the trigger 15 is in a single state, a unit appears at the output of AND 52, which through the elements OR 47 goes to the inputs of register writing 49. In this case, information from register номером number пере is copied to register number (/ -1). At the same time, the unit from the output of the element And 52 enters the subtracting input of the register 56 of the queue of applications, shifting the unit from

The 2 nd output for (/ —1) -th, as well as the unit from the output of the AND 52 element through the OR 43 element and the delay element 44 enters the zero input of the trigger 15, setting it to the zero state. If in block 14 of the formation of the queue there are no applications (at the first output of the register 56 of the request queue is one), then as soon as the trigger 15 is set to one, the unit at the output of the AND 42 of the queue forming unit 14 will receive a unit that through the element OR 43 and the element 44 the delay will arrive at the zero input of the trigger 15 and reset it to the zero state.

The statistical characteristics of the operation of the QS simulated by this device are calculated by a known method based on meter readings.

Claims (1)

Claim A device for simulating queuing systems containing a code setting block, two encoders, two code registers, a block of elements NOT, a subtraction block, a register of free devices, a first multiplexer, a register of orders, a block of random pulse generators, three elements of OR, a block of bar elements, a block random time delays And the first block of elements And, the adder, the counter of unserved applications, the counter of the total number of applications, the control unit and the block definition feature, containing four elements And, the element OR, three elements NOT, and in the characteristic definition block, the output of the first element AND is connected to the first input of the second element AND and the input of the first element NOT, the output of which is connected to the first input of the third element AND, the second inputs of the second and third elements AND and the input of the second element are NOT connected and connected to the output of the sign bit of the subtraction unit, the output of the second element NOT of the attribute definition unit is connected to the first input of the fourth element And, the second input of which and the third inputs of the second and third elements And are connected and connected to the output end in reading the subtraction unit, the output of the second element AND the attribute detection unit is connected to the first input of the OR element of the attribute detection unit and the zeroing input of the register of free devices, the output of the fourth Element I is connected to the second input of the OR element of the attribute detection unit, the output of which is connected to the input of the third element NOT, the control unit contains two differentiating elements, three triggers and two elements And, the outputs of the first and second differentiating elements are connected respectively to the zero inputs of the first and second triggers whose direct outputs 9 1485263 ten connected to the first inputs of the first and second elements And the control unit, respectively, and the inverse outputs of the first and second flip-flops are connected respectively to the second inputs of the second and first elements And the control unit, the output of the first element And connected to the single input, and the output of the second element And to zero the input of the third trigger of the control unit, the outputs of the first encoder are connected respectively to the bit inputs of the first register of the code, the bit outputs of which through the block of elements are NOT connected to the information ones The first group of the subtraction unit, the information inputs of the second group of which are combined respectively with the information inputs of the first group of the adder and connected to the bit outputs of the register of free devices, the bit inputs of which are connected respectively to the outputs of the first multiplexer and the outputs of the code setting block, the information inputs of the first group the multiplexer is connected respectively to the outputs of the adder, the information inputs of the second group of which are connected respectively to the information and the outputs of the subtraction unit and the inputs of the first element AND the characteristic definition unit, the output of the first element OR is connected to the write enable inputs of the first register of the code and register of orders and the single input of the first trigger of the control unit, the output of the third element NOT of the characteristic definition unit is connected to the control input of the prohibition block , and the first input of the second element OR 'of the device is connected to the output of the fourth element AND the tracer detection unit, the output of the second element OR of the device is connected to the resolution input and the register of free devices, the bit outputs of the order register are connected respectively to the information inputs of the prohibition block and to the information inputs of the first block of elements And, the input of the first differentiating element of the control unit is connected to the output of the end of the subtraction of the subtraction unit, the direct output of the third trigger of the control unit is connected to the permission input subtracting the subtraction unit and the first control input of the first multiplexer, and the inverse output of the third trigger of the control unit is connected to the input of the bit Solutions of summation of the adder and the second control input of the first multiplexer, the single input of the second trigger of the control unit and the input of the write resolution of the second code register are connected to the output of the third OR element, and the input of the second differentiating element of the control unit is connected to the output of the summation end of the adder and the second input The second element OR device, the outputs of the prohibition block are connected respectively to the inputs of a block of random time delays, the outputs of which are connected respectively to the inputs of the third OR element and to the inputs of the second encoder, the outputs of which are connected respectively to the bit inputs of the second register of the code, the bit outputs of which are connected respectively to information inputs of the second group of the adder, the outputs of the first block of elements And are connected respectively to the counting inputs of unserved applications, different so that, in order to expand the functionality of the device by simulating a queue, it additionally contains a second multiplexer, a second block of elements AND, a trigger block forming a queue, and the block forming the queue contains the first, second, third, fourth and fifth elements AND, the element OR , the first and second elements are NOT, the first and second elements of delay, the order queue register, the group of elements AND, the group of elements OR, the group of multiplexers, the group of registers of application codes, the group of blocks of elements of delays, the first the first, second, and third I moves are combined and connected to the device’s direct trigger output and to the control input of the device’s second multiplexer; the second input of the first element E of the queuing unit is connected to the output of the first order queue register, the second input of the second I element is combined with the first inputs the fourth and fifth elements And and is connected to the output of the third element And the block definition feature and to the first inputs of the elements And group block forming the queue, the second inputs of the fourth and fifth e The AND elements are combined with the second inputs of the AND elements of the group and with the control inputs of the multiplexers of the group of the queuing unit and connected to the inverse output of the device trigger and the control input of the second unit of the AND units, the output of the third element NOT of the characteristic determining unit through the first element of the queuing unit connected to the second input of the third element AND the block forming the queue, the output of which is connected to the first input of the element OR, subtracting the input of the register of the queue of applications and with the first input of the OR block group, the output of the first Q block of the queue shaping unit is connected to the second input of the OR block of the queue shaping unit, the third input of which is connected to the output of the second AND element, and the output of the ILY element of the queue shaping unit through the first delay element is connected to zero device trigger input, times11 1485263 12 the row outputs of the queue register are connected respectively to the third inputs of elements AND groups, the outputs of which are connected respectively to the second inputs of the OR elements of the group, the overflow output 5 of the order queue register is connected to the third input of the fifth element AND of the queuing unit and through the second element NOT to the third input of the fourth element And the block forming the queue, the output of which through the second delay element is connected to the summing input of the queue of requests, the output of the fifth element And the block forming the queue Connected to the control input of the first block of elements AND device, the outputs of the elements OR of the group of the queuing unit are connected respectively to the inputs of the resolution of writing registers of application codes of the group, the bit inputs of which are connected respectively to the outputs of the same multiplexers of the group, the information inputs of the first group of which are connected respectively to bit outputs of the register of applications of the device, the information inputs of the second group of the last multiplexer of the group of the queuing unit group are combined and Connected to the zero potential bus, the bit outputs of the group code registers are connected to the inputs of the corresponding group delay unit, the Ζ-ΓΟ outputs of the group delay unit (ζ = 2, K) are connected respectively to the information inputs of the second group of multiplexers of the group forming the queuing unit, the outputs of the first delay unit the groups are respectively connected to the information inputs of the first group of the second multiplexer of the device, the information inputs of the second group of which are connected to the outputs of the random pulse generator block, and the outputs of the second multiplexer are connected respectively to the digit inputs of the device's demand register, the inputs of the first OR element of the device and the inputs of the first encoder, the device’s single trigger input is connected to the output of the device’s summing up output, the information inputs of the second AND block of the order register, and the outputs to the counting inputs of the total number of applications. 1 1485263 FIG. five 1485263 ίξ «4 | <3 K? 5 G \ ΗI Reset