SU962970A1 - Device for simulating mass servicing systems - Google Patents

Description

The invention relates to computing technology, in particular, to 1M devices for modeling large-scale ones, and can be used to optimally select the number of service systems in complex system phases to minimize their total cost, taking into account the limitation on the residence time of the system under study. A device for simulating queuing systems is known, comprising blocks of models of branches and vertices made on AND, OR, and triggers, connected on a typed field in accordance with the topology of the graph. 1, This device does not allow to simulate multichannel queuing systems, determine the number of service channels in Lazy and investigate it with combinatorial combinations of queue lengths in phases. The closest to the proposed technical entity is a device for simulating queuing systems, containing m blocks of simulating the phase of the queuing system, an optimization block and a generator of random pulse generators, the outputs and inputs of which are connected to the dial field in accordance with the queuing system phase , each block of modeling the phase of the queuing system contains the first, second and third elements OR, n elements AND, n triggers, n generators of the Time intervals, n items NOT, n differentiating elements, the first and second decoders, the switch, the counter and the reversible counter, summing the INPUT which is connected to the output of the first OR element whose inputs are block inputs, the reverse outputs of the reverse counter are connected to the inputs of the second element OR, the output of which is connected to the first inputs of the elements AND, the second inputs of which are connected to the output of the flip-flops, the inputs of which are connected to the outputs of the first decoder, the inputs of which are connected to the bits in moves counter, a summing input coupled to an output switch, the first input of which is input to a phase other of its inputs connected to the outputs of the second

the decoder, whose inputs are connected to the RZD outputs of the reversible counter, the subtracting input of which is connected to the output of the third OR element, whose inputs are combined with the inputs of random time interval generators and connected to the outputs of the AND elements, , the inputs of which are connected to the outputs of random time interval generators and to the inputs of differentiation elements, the outputs of which are the outputs of the block, the fourth input of every 1st element I is connected to the outputs ode each Sp-1) -th random time interval generator, the optimization block contains the first, second, third and fourth elements OR, the first and second elements And, the first and second elements of the ban, the first, second, third, fourth and fifth differentiating elements , first, second and third delay elements, first, second and third triggers, decoder, register, first, second and third counters, first, second and third adders, the inputs of the first OR element are the inputs of the block and its output is connected to the input first item zap The output whose output is connected to the input of the first counter, the bit outputs of which are connected to the decoder, (n-) whose outputs are connected to the inputs of the second OR element, whose output is connected via the first differentiating element to the counting input of the third trigger and to the single input of the second trigger The zero output of which is connected to the prohibitory input of the second prohibition element, the other input of which is connected to the output of the prohibition element of the generator unit, the input of which is connected to the output of the clock generator, and The main input is connected to the prohibitory input of the first prohibition element of the optimization block and the single output of the first trigger whose single input is connected to the zero input of the second trigger, through the second differentiation element to the n-th output of the decoder, the input of the first delay element and the first inputs of the third and fourth elements OR , the second inputs of which through the third and fourth elements of differentiation are connected respectively to the single and zero outputs of the third trigger and the first inputs of the first and second elements And the other inputs of which are connected to the output of the second barring element, and the outputs of the elements And are connected to the inputs of the second and third counters, respectively, the second inputs of which are connected to the outputs of the third and fourth elements OR, and the outputs of these meters are connected to the first and second inputs of the first adder , the third input of which is connected to the output of the first delay element, the second input of the first counter, the input of the second delay element, and the output of the first adder is connected to the first input of the second adder, the second input o is connected to the output of the second delay element and the register input, the third input of the second adder is connected to the output of the first counter, and the output is connected to the first input of the third adder, the second input of which is connected to the register output, and the output is connected to the fifth differentiation input, the output of which is the output of the optimization block, and through the third delay element is connected to the zero input of the first trigger.

The described device makes it possible to simulate multichannel queuing systems with the calculation of the number of service channels in each phase according to a given probability of the time spent in the system. One of the most relevant and important requirements for queuing systems is to minimize the total cost of the system while maintaining the specified quality characteristics, i.e.

and

IC; X- min,

1st

where C- is the cost of one service channel in the i-th phase;

number of service channels

i

in the i-th phase;

the number of phases of the QS,

P

.

where 1d is the allowable time of stay in the QS; R - given the probability of pre vyhod of a quotation in the QS.

Optimization of networks (for example, data transmission networks) by the indicated criterion is an important national task for Gz.

The disadvantage of such a device is the impossibility of minimizing the cost of the system under study.

The purpose of the invention is to expand the functionality of the device due to the optimal choice of the number of service channels in the phases of the system according to the minimum cost criterion with the probable limitation of the service time of the request. the system.

This goal is achieved in that a device for simulating a queuing system comprising m service phase simulation blocks, an optimization block and a random pulse flow generator block containing a clock pulse generator, a prohibition element and a group of random pulse sensors, each the first, second and third elements OR, n elements AND, n triggers, n generators of random time intervals, n elements NOT and n differentiating elements / first and the second decoders, a switch, a counter and a reversible counter, the summing input of which is connected to the output of the first element OR, the bit outputs of the reversible counter are connected to the inputs of the second element OR, the output of which is connected to the first inputs of the elements AND, the second inputs of which are connected to the outputs of the trigger, the inputs of which are connected to the outputs of the first decoder, the inputs of which are connected to the bit outputs of the counter, the input of which is connected to the output of the switch, the group of its information inputs are connected to the outputs of volts decoder, the inputs of which are connected to the bit outputs of the reversible counter, subtracting the input of which is connected to the output of the third element OR, the inputs of which are combined with the inputs of random time interval generators and the third inputs of which are connected to the outputs of the elements NOT, whose input connected to the outputs of the random time interval generators and to the inputs of the differentiation elements, the outputs of which are the outputs of the block, the fourth input of the i-element of the AND (, n) is connected to the output

{.n-lj-ro random time interval generator, the optimization block contains four OR elements, two AND elements, two prohibition elements, five differentiating elements, three locking elements, three triggers, a deishfrator, a register, three counters, the first sug plate, voltage divider and comparison circuit, the output of the first element OR is connected with the prohibiting input of the first prohibition element whose output is connected to the input of the first counter, the discharge outputs of the counter are connected to the inputs of the digger, and the (n-1) outputs of which are connected to the inputs of the second the OR element, the output of which is connected through the first differentiating element with the counting input of the third trigger and the zero input of the second trigger, the unit output of which is connected to the inhibit input of the second inhibit element, whose information input is connected to the output of the block inhibit element

random flow generators of pulses and inputs of a group of random pulse sensors, the input of a prohibition element of a generator of random generators of pulses is connected to the output of a clock generator, and the prohibiting input is connected to the prohibiting input of the first prohibition element of the optimization block and the zero output of the first trigger, the zero input of which is connected to unit input of the second trigger, through the second differentiation element with the nth output of the decoder, the input of the first delay element and the first inputs of the third and of the third OR elements, the second inputs of which through the third and fourth differentiation elements are connected to the zero and single outputs of the third trigger, respectively, and the first inputs of the first and second And elements, the second inputs of which are connected to the output of the second prohibition element, and the outputs of the And elements are connected to information the inputs of the second and third counters, respectively, the control inputs of which are connected to the outputs of the third and fourth elements OR, respectively, and the outputs of the counters are connected to the first and second The inputs of the first summer, the control input of which is connected to the output of the first delay element, the control input of the first counter and the input of the second delay element, and the output of the first adder are connected to the first input of a voltage divider, the control input of which is connected to the output of the second delay element and the register input, the second input of the voltage divider is connected to the output of the first counter, and the output is connected to the first input of the comparison circuit, the second time of which is connected to the output of the register, and the output is connected to the input The differentiation element, the outputs of the random pulse sensors of the random pulse flow generator block, the inputs of the first OR elements, the control switch input and the outputs of the differentiating elements of the service phase simulation blocks and the inputs of the first OR elements of the optimization block are connected to the topology of the phases of the queuing system, in each block of the simulation of the service & functions, a register is entered, the group of the bit inputs of which is connected to the bits

Claims (2)

1. Author's certificate of the USSR 347763, c. 06 G 17/48, 1962. 2. USSR author's certificate on application 2830494, C. 06 G 7/46, 1979 (prototype).