SU1462344A1 - Device for forming the route of message in homogeneous computing system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-performance matrix, pipeline, systolic, vector and other processors, in which the data is processed in a computing environment during information processing. The purpose of the invention is to increase the speed of the device while reducing hardware costs. In order to achieve this goal, the unit 3 additions information is additionally entered into the device, which allows organizing calls only to those buffer blocks 1.1 ... 1.9 that contain messages received for service and thus eliminate empty loops. 2 z.p, f-ly. 6 Il.

Description

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The invention relates to computing technology and can be used in the construction of high-performance matrix, pipeline, systolic, vector and other processors, in which data is processed in a computing environment during information processing.

The aim of the invention is to increase the speed of the device while reducing hardware costs.

Figure 1 shows the functional diagram of the proposed device for forming a message route in a uniform computing system; figure 2 is a functional diagram of the buffer storage unit; FIG. 3 is a functional block diagram of information reading; Fig O4 - functional block diagram of the synchronization; FIG 5 is a message format; Fig. 6 illustrates an example of data paths between the processor elements (PEs) of the modular computing system for the known and proposed technical solutions.

The device for generating a message route in a homogeneous computing system (Fig. 1) contains a group of buffer storage blocks 1.1 - 1.9, block 2 of memory constants, block 3 of information reading, register 4, demultiplexer 5, first block 6 of comparison, second block 7 comparison, block 8 elements AND, block 9 elements OR, element OR X unit 11 synchronization, element AND 12 ,, j group of inputs 13.1-13.9 of the device and group of outputs 14.-1-14.9 of the device.

Buffer storage unit 1.1 (i f7 (figure 2) contains a block of registers 15.1-15. By Hgde K - queue depth), the block of switches 16 -.

.16 (K-1), the second block of elements And 17.1 17.K, demultiplexer 18, element I-NOT 19, t rigger 20, element OR 21, one-shot 22, first block 23 of elements I. Information reading unit (Fig. 3 ) contains a block of triggers 24.1-24.9, the first block of elements And 25.1-25.9, the second block of elements And 26., a block of one-shot

 27.1-27.9, element AND 28. The synchronization unit 11 (FIG. 4) contains a clock pulse generator 29, a counter 30, a decoder 31.

The purpose of the main functional elements of the device is as follows.

The group of buffer storage units 1.1-1.9 is intended for queuing data from eight neighboring devices to its own processor element (PE) for transmitting information to neighboring devices. Block 2 of memory constants is designed to store a code (identifier) that identifies the location of the device in the matrix of processor elements (homogeneous computing system). Unit 3 to count information is intended for cyclical polling and sampling of information from the group of buffer storage units 1.1-1.9. Register 4 is designed to store address and operational (semantic) pieces of information during the analysis and selection of the direction of information transfer.

The demultiplexer 5 is intended for switching a message in one of eight directions to neighboring devices (processor elements). The first 6 and second 7 comparison blocks are designed to analyze the address portion of the message received for service. The block of 8 elements And is intended to enable the recording (transmission) of the operational (semantic) part of the message, if the address parts of the device coincide with the incoming message. The synchronization unit 11 is designed to set the pulse sequences dp synchronization operation of the device

The purpose of the elements of the i-ro buffer storage unit (i 1,9) (figure 2) is as follows.

The block of registers 15.1-15. K is intended for storing and queuing incoming messages for servicing; The j-th element And (j 1.K) of the block And elements 17.1-17.K is designed to form a control-, c, signal that identifies the zero state of the corresponding register 15.1. A switch box 16.1-16. (K-1) is intended for KOMJ mutation of information of incoming messages to be written into the corresponding register register register 15.1.

15.K. The demultiplexer 18 is intended for switching (distributing) incoming messages for servicing in the order of their arrival in the block of registers 15.1-15. K depending on the queue occupancy.

The IS-NE element 19 is intended to generate a control signal of the presence in the block of the buffer memory of a message for its analysis and issue either to the neighboring system devices or to be serviced by a fixed processor element. The trigger 20 is designed to control the process of recording and shifting information in a block of registers 15.1-15. A single vibrator 22 is designed to form a zeroing pulse.

a heterogeneous structure, each processor element of which is connected in eight directions with adjacent processor elements. The transfer of information between any PE computing system is carried out in a transient manner along a minimal physical path through other PEs.

TO array, for example in eight possible directions using the proposed device.

The incoming information (messages on any of the directions is recorded

15 to the corresponding buffer storage unit 1.1 (i 1.9) (FIG. O. The information about the transmitted message is entered as from eight neighboring similar devices of the system.

trigger 20 after the organization of the shift of 20 gz own processor

element (PE) computing system. Each PE of the computing system (proposed device) is assigned an address consisting of 25 two codes defining the location of the PE, and hence the device in the PE matrix, and corresponds to the row number and column number (Fig. 6). This address is iden

information in the register block 15.1 - 15.К.

The purpose of the elements of the information reading unit 3 (FIG. 3) is as follows.

The trigger block 24.1-24.9 is designed to store the code that determines in the i-M code bit the presence of a message in the corresponding block

element (PE) of the computational system. Each PE computational system (the proposed device) is assigned an address consisting of 25 two codes defining the location of the PE, and hence the device in the PE matrix, and corresponds to the row number and column number (Fig.6). This address is ideal.

buffer memory. The first block is an element-30 identifier in relation to other

a homogeneous structure, each processor element of which is connected in eight directions to adjacent processor elements. The transfer of information between any PE computing system is carried out in a transit way along a minimal physical path through other PEs.

array, for example in eight possible directions using the proposed device.

The incoming information (messages) on any of the directions is entered

to the corresponding buffer storage unit 1.1 (i 1,9) (FIG. O. The information about the transmitted message is entered as from eight neighboring similar devices of the system.

 rz own processor

element (PE) computing system. Each PE of the computing system (proposed device) is assigned an address consisting of two codes defining the location of the PE, and hence the device in the PE matrix, and corresponds to. row number and column number (Fig.6). This address is iden

Commerce And 25.1-25.9 is designed to enable the writing of the next status code of a group of blocks 1.1-1.9 of the buffer memory into the block of triggers 24.1 24.9. The second block of elements AND 26.1 to 26.9 is intended for the sequential generation of signals and the interrogation of the corresponding blocks of the buffer memory; The i-th one-shot (i 1,9) block of one-shot 27.1-27.9 is designed to generate a pulse to zero the corresponding trigger 24.1 after reading the message from the corresponding buffer memory block.

Element And 28 is intended to form a zero state signal of the block of triggers 24.1-24.9 and enable the recording of the next status code of the group of buffer storage blocks 1.1-1.9.

Consider the operation of a device for forming a message route in a homogeneous computing system.

In the initial state, the elements of the device are in the zero state.

The modular computing system is a regular

50

g

computing system devices.

The choice of the direction of transmission of the incoming message in the proposed device is as follows.

The address part of the incoming message (Fig. 5) with the address of this device, according to the row and column numbers, defines one of nine possible directions (one for processing this PE and eight others for neighboring PE).

Let A be the code of the line number of the receiver of information; In - code number 5 column receiver information. Then the code of the address part of the message can be represented as AB, where A is the sign of concatenation (concatenation) of the two codes. Accordingly, the device address code Q (identifier) can be represented as C; D, where C is the location code of the device in the row of the matrix PE, and D is the location code of the device in the column of the matrix PE. The choice of the message transmission direction is determined by the following rule:

C - A D - B,

That is, the selection of the message transmission direction is determined by the minimum physical distance between the information transmitter device (CD) and the receiver device (AV) information.

Then the message transmission in the vertical direction is defined as follows: if C A is up; if C - A - down; if C - A - stop.

62

25 (6 7 2) L (2 5)

-5.3 - 25 (5 2) L (3: 5)

 - 44 - 25 (4 2) / (4 g 5)

-35 - 25 (3 2) L (5 5)

- 25

25 (2 2) / (5 5)

The considered message transfer procedure is aimed at minimizing the physical path between the processor and the processing elements of the computer system.

Information from neighboring PEs of a single structure (for example, when transferring data between the processor elements in the systolic array) is sent to the proposed device for its analysis and transit output to the appropriate channel (direction) of the device. This information is fed to the inputs 13.1-13, devices for transferring it into buffer storage units 1.1-1.9. In addition to the address and operational (semantic) information on the corresponding input 13.1 (1 1.9) comes from neighboring PE clock pulse, by which the message is entered into one of the registers 15.1-15. To the block (figure 2) In the buffer storage In block 1.1 (1, 1.9), as the message arrives, they begin to fill in the registers, beginning with the first, as follows. Since the trigger 20 is in the zero position, the signal of the logical unit from the inverse output of the trigger 20 is fed to the control inputs of the switch unit 16.1 -; 16 (K-1) and thus allows the passage of information from the outputs of the demultiplexer 18 through the corresponding switches 16.1-16. (K-1) to the information inputs of the registers.

Horizontal movement is determined by the rule: if D B is left; if D i B - to the right; if D In - stand.

For example, it is required to transmit a message from a device having an address in the matrix of the PE 62 (Fig. 6) to the device with the address 25,

The procedure for selecting the message transmission direction can be represented as follows:

right right right

25

thirty

At the initial time, the block of registers 15.1-15. K is in the zero state, and the signals of the logical unit are at the output of the elements AND 17.1-17.K. These signals (code) are sent to the control input of the demultiplexer 18 and enable. Writing of the incoming message to the register 15о1. The state of this register is different from zero, which changes the code received to the control 35 input of the demultiplexer 1B and prepares its output to write the queue message to register 15.2, etc.

When entering information into fern storage blocks, a logical unit signal appears at the output of the NAND element 19 (Fig. 2) of the corresponding block. This signal (signals) from the outputs of the buffer storage units comes, first, through the element OR 10 (Fig. 1) to the control input of the synchronization unit 11, and, second, to the information inputs of the information reading unit. 50 The signal of the logical unit at the control input of the synchronization unit 11 (FIG. 4) allows the generation of pulses at the output of the generator 29 for synchronizing the operation of the device.

55 Since the triggers 24.1-24.9 are in the zero state, the first clock pulse coming from the output of the synchronization unit 11 to the input of the information reading unit 3

The SRI (FIG. 3) through the AND 28 element allows the recording of information on the state of the buffer storage blocks 1.1-1.9 through the AND 25.1 25.9 block of elements into the trigger block 24.1-24.9.

When writing information to the trigger block 24.1-24.9, its state is different from zero and therefore the output of the AND 28 element is a logical zero signal, which prohibits the recording of information from the inputs of the block 3 reading information to the trigger block 24.1-24.9 before the end of the maintenance procedure for the recorded code . Suppose that the block 010100000 is recorded in the block of triggers 24.1–24.9, which corresponds to the presence of messages in the second and fourth buffer storage blocks 1.1–1.9 of the group. Since the direct output of the trigger 24.1 of the information readout block 3 (FIG. 3) contains a logical zero signal, the first clock pulse of the next pulse sequence from the synchronization block 11 through element 26.1 will read the information from the first block 1 o 1. This impulse, entering the inputs of the AND 26.1-26.9 unit, will pass through the AND 26.2 element to the output of the information reading unit 3 and from its output to the control input of the buffer storage unit 1.2 (Fig. 2). The impulse arriving at the control input of the unit 1.2 permits the output of information through the block of elements AND 23 from the output of the register 15.1, in which the first message is located. In addition, the control pulse sets the trigger 20 to one state, the signal from the direct output of which allows information to be shifted in the block of registers 15.1-15. K through switches 16.1-16, (K-1),

Information from the outputs of the register 15 of the buffer storage unit 1.2 through the block of elements AND 23 (figure 2) through the block 9 of elements OR (figure 1) is fed to the information input of the register 4. The received information is entered into the register L by the clock pulse from the output of the synchronization block 11 After the information has been recorded in register 4, the pulse shifted to the control input of the 1о2 block is cut off, information is shifted in the block of registers 15.1-15.K (Fig. 2). Outlet Oscillator

22, a pulse is formed that sets the trigger 20 to the initial (zero) state and thereby enables the recording of messages arriving in the buffer storage unit 1.2.

The information recorded on the second clock pulse (Fig. 5) contains the operational (sense) part and the address part. In this case, the address part contains two fields defining the location of the information receiver in the PE matrix vertically and horizontally. Address information is fed to the inputs of blocks 6 and 7 of the comparison. The third clock pulse of the sequence from the output of block 2 of memory constants to the second inputs of blocks 6 and 7 of the comparison receives an identifier (code), which determines the location of this device in the matrix of processor elements.

Depending on the ratio of these two codes, the direction is formed

further transmission of the message. When the codes coincide both vertically and horizontally, the Equal Signals are formed at the outputs of the first 6 and second 7 comparison blocks. These signals at the output of the element And 12 form a signal identifying the fact that the received message is intended for this processor element. This signal, received at the control input of the 8-element block And simultaneously with the clock pulse, permits the passage of semantic information to the output 14.1 of the device for recording, for example, in the RAM of the processor element for the purpose of further processing the incoming message

In the case of a different combination of code comparison (signals from the outputs of blocks 6 and 7 of the comparison are sent to the control input of the demultiplexer 5), the decisive rule for choosing the direction of further message transmission is implemented by the decoder of the demultiplexer 5. Communication with clock pulses through the demultiplexer 5 and one of outputs 14.2 -14.9 comes to one of the neighboring similar devices of the system.

After issuing a control signal to read information from the second buffer storage unit 1.2, the output of the one-shot 27.2 of the information reading unit 3 generates a pulse that sets the trigger 24.2 to the zero state and thereby interrogates the availability of information in other buffer storage units. Therefore, the first clock pulse of the next sequence arriving at the clock input of the information readout unit 3, gives a pulse to read information from the fourth buffer storage unit 1.4, since the code of the unit is stored in the 24.1–24.9 trigger unit 0001000СGO. Further, the device functions as described by the JMV.

When zeroing block triggers 2L.1-24.9 of block 3 of reading information (Fig. 3), the next clock pulse through the AND 28 element enters the control inputs of the elements; AND 25.1-25.9 and permits the recording of an alternate code to service those buffer storage units 1.1-1.9; in which there are messages for: transmission. Further, the device operates as described.

When messages are sent to neighboring devices and their own PE, the registers 15.1-15. To the buffer memory of blocks 1.1–1.9 are in the zero state. At the outputs of the elements And 17.1-17.K are the signals of a logical unit that arrive at the input of the element AND-NOT 19 and form a logic zero signal identifying the absence of a message in the corresponding buffer storage unit .1.i (i - 1.9) logical zero from the control, outputs of buffer storage blocks 1.1-1.9 at the output of the element OR 10 form a logical zero. This signal inhibits the formation of clock pulses at the outputs of the block: ka l l synchronization, and the device finishes operation.

Claims (2)

Invention Formula .one . Forming device message path in a uniform computing system containing nine buffer storage blocks, a block of constants, a register, a multiplexer, two comparison blocks, a block of AND elements, a block of OR elements, an OR element, a synchronization block, and an element, first through ninth inputs 0 five 0 Jq 55 The storage memory blocks are from the fifth to the ninth informational inputs of the device, respectively, the first control inputs from the first to the ninth buffer storage blocks are the first to ninth control inputs of the device. accordingly, the information outputs of the first through ninth buffer storage blocks are connected from the first to the ninth inputs of the block of OR elements, from the first to the ninth control outputs of the buffer 5 storage blocks are connected with the first to ninth outputs of the OR element, respectively, output the block of elements OR is connected to the information input of the register, the synchronization input of which is connected to the first output of the synchronization block, the start input of which is connected to the output of the OR element, the second output of the synchronization block is connected to synchronization block memory block of constants, the output of which is connected to the first inputs of the first and second comparison blocks, respectively, the outputs of the first and second register groups are connected to the second inputs of the first and second comparison blocks, respectively, the outputs of the third register group and the third output of the synchronization block are connected to bits first The 5 inputs of the elements And, the outputs of the first, second and third groups of the register and the third output of the synchronization block are connected to the bits of the information input of the demultiplexer, the output is Greater, Less and Equal to the first and - the second comparison block are connected from the first to the sixth control inputs of the demultiplexer respectively the outputs are equal to first and 5 of the second comparison unit is connected to the first and second inputs of the element AND, respectively, the output of the element AND is connected to the second input of the block of elements AND, whose output is the first output of the device, from the first to the eighth outputs of the demultiplexer is from the second to the ninth outputs of the device, respectively, characterized in that, in order to improve speed while reducing hardware costs, an information reading block is introduced into it, the first to ninth outputs of which are connected to the second control inputs from the first to the ninth buffer storage blocks, respectively, from the first to the ninth information inputs of the information acquisition block are connected to the control outputs from the first to the ninth buffer storage blocks, respectively, the synchronization input of the information readout block is connected to the fourth output of the synchronization block. 2. The device according to claim 1, characterized in that the buffer storage unit contains K registers (where K is the queue depth), {K-O switches, K elements AND, demultiplexer, block of elements AND, trigger, one-shot, element OR , and the NAND element, the information input of the demultiplexer being the information input of the block, the i-th output of the demultiplexer (i 1, K-1) connected to the first information input of the i-ro switch, K-th output de the multiplexer is connected to the information input of the K-th register, the output of the j-ro register (j 2, K) is connected to the second information stroke (j-1) th switch output i-ro switch connected to the data inputs of the register i-ro, first register output connected to a first the input of the AND block whose output is the information output of the block, the output of the nth register (t 1, K) is connected to the input of the t-th element AND, the outputs K of the elements AND are connected to the control inputs of the demultiplexer and the inputs of the AND-NES element whose output is the controlling output of the block, the first and second inputs of the STI element are the first and the second control inputs; block respectively, the first input the OR element is connected to the installation input of the trigger unit and to the second input of the AND block, the output of the OR element is connected to the synchronization inputs of all registers, the forward trigger output is connected to the single-oscillator and the first control inputs of all switches, the inverse output the trigger is connected to the second control inputs of all the switches, the output of the one-shot is connected to the input of the zero setting of the trigger. 3, the device according to claim 1, characterized in that the information reading block comprises a trigger block, the first and second blocks of the And elements, the single-vibrator block and the And element, and the information inputs of the information reading block are connected to the first inputs of the first block of And elements, the outputs which are connected to the installation inputs of the trigger unit, the forward outputs of which are connected to the first inputs of the corresponding element AND of the second block of elements AND, the outputs of which are connected to the corresponding outputs of the information reading unit and the inputs of for one-vibrators whose outputs are connected to the corresponding reset inputs of the trigger block, the inverse output of the 1st trigger of the trigger block (i 1 ..., 9) with the inputs from (i - «- 1) -ro by the ninth element II the block of elements And with the inputs of the element And, the output of which is connected to the second inputs of the elements And the second block of elements And, the synchronizing input of the information reading block is connected to the clock input of the element And and the corresponding inputs of the elements And the second block of elements And, ABOUT ft sh  " eight Ttg &one Thebes. 2 29 Fig 3 t / JO : J7 Fi &. Codep ufioe register Meaning informational FIG. five eleven A I A I / h I I UCH I five 21 F 12 1gL / 5 13 22 F 12. eight AND 2-5 15 sixteen 24 / 26 hky ahskg - J / - JZ - JJ - JV - 55 J5 - : D one 42 51 25 1b 3 52 TsCh 53 45 five 6 55 56 : j jc3cj c3c: x 61 mjL DZ Device address of the receiver Vertical address of the vertical patriz s PE five AND 15 sixteen 24 / 26 TsCh 45 6 55 56 6 65 66