SU1522232A1 - Device for switching messages in data transmission networks - Google Patents

Abstract

The invention relates to communication technology and computing technology, in particular to the construction of message switching nodes in data networks. The purpose of the invention is to increase throughput by reducing the amount of transmitted service information. The goal is achieved by applying a disjoint code to the path of each message in the message header to record. This allows a significant reduction in the length of the service part of the message. For this, an adder, a register, an encoder, two counters, a decoder, a delay element, a frequency divider, two triggers, and AND, OR logic elements are entered into the device. The device provides a message in the selected direction and a record in the header of the new value of the code word passed by the message path. The device uses the properties of disjunctive codes to prevent messages from re-passing the data network of a previously traveled path. 2 ill., 1 tab.

Description

The invention relates to communication technology and computing technology, in particular to the construction of message switching nodes in data networks.

The purpose of the invention is to increase throughput by reducing the amount of transmitted service information.

Figure 1 shows a diagram of an apparatus for switching messages in data networks; figure 2 - diagram of the pulse distributor.

The device for switching messages in data transmission networks contains the first register 1, the adder 2, the comparison circuit 3, the first element AND 4 ,,

the sixth register 5, the second group of 6 elements AND, the first element OR 7, the second element And 8, 5 5 register 9, the first decoder 10, the distributor II pulses, the first group 12 elements And, the second register 13, element 14, the first counter 15, the second decoder 16, the first delay element 17, the second delay element 18, the third register 19, the pulse shaper 20, the third element 21, the comparison unit 22, the first trigger 23, the frequency divider 24, the second counter-25-25 number of characters, the second element OR 26, fourth register 27, element And 28, the generator 29 clock pulses second trig er 30, the fifth element

QI

yu yu

with

ISD

I And 31, the sixth element And 32, the third group of 33 elements And, the encoder 34, the first fourth governing

inputs 35 - 38, launch input 39, in: formational input 40 and informational; output 41,

I Distributor 11 pulses contains register 42, generator 43, element AND 44, group of 45 elements AND, element OR 46 and trigger 47,

In the initial state, all the device registers were reset, in the first discharge register 42 of the distributor 1 1 pulses recorded 1, the counters are in the zero state, the trigger 23 is in the zero state (low potential is removed from the output), and the trigger 30 - in a single state (high potential is removed from the first move)

In preparation for operation, a summary code of numbers previously passed by the message of network switching nodes, which is recorded in the code word A in register 1, is entered into the device at input 35, and at the same time, input codes of switching nodes that are allowed as transit (Transit message from the same time, the code of the number E A L B is output to the output of the adder 2, which is fed to the second inputs of the comparison circuit 3, the first inputs of which are the code of the number A, two numbers are compared by the clock frequency signal You, which enters the 3 comparison circuit from the generator 29 clock pulses through the open element And 28, If as a result of bitwise comparison, a low potential is output from the output of the comparison circuit 3, indicating that the B number at the previous stages of the message transmission the network participated in the formation of the sum A, t „e, the message had already been served once at node B, Otherwise (EfA), the output of the comparison circuit 3 gives a high potential. In addition to Toroj, the clock frequency impulse goes to the comparison block 22, which compares numbers C and De If D C, j, then a potential appears at the output of block 22, otherwise, a low potential appears at the output. Thus, if conditions and D C are fulfilled simultaneously, then high potentials with

switching device to the address-: d of the comparison circuit 3 and the comparison block 22

 the recipient of the message, the input number 37 codes for the number of messages from the input buffers of the corresponding switching nodes are entered, the maximum allowable load code for input 38 The codes of the valid switching nodes as a sequence

35

the value of the first counter 15 is determined by the unit and via open: elements 4 and 8 in the first parts of registers 5 and 9, codes E and B, respectively, are recorded. If at least one of these conditions is not met; the counter value does not change and AND 4 and 8 remain closed. "Further, the clock signal delayed in the delay element 17 delays the code words in the i 3 and 195 registers, i.e. if words were written down before

words in

AT

g

B; recorded

40

the value of the first counter 15 is determined by the unit and via open: elements 4 and 8 in the first parts of registers 5 and 9, codes E and B, respectively, are recorded. If at least one of these conditions is not met; the counter value does not change and AND 4 and 8 remain closed. "Further, the clock signal delayed in the delay element 17 delays the code words in the i 3 and 195 registers, i.e. if words were written down before

E J oki, - 5-1 i V;, - С -;

THEN now there will remain f ,, E ;;,., In

45

and (/) 3 С

WITH.

in register 13, codes of the number of messages in the form of a sequence C, C, ..., C; In register 19, the code of maximal load in the form of a number D is in register 27. The bitness of the numbers A and Bi, as well as D and C; match up. The adder 2 performs a bitwise addition of the number A from register 1 with the first number recorded in register 13, the addition is carried out in accordance with the rule 1 L 1 1., 1 L O 1, i.e. adder 2 is a set (by the number of bits of the number A) of the two-input OR circuits,

Upon completion of input codes

35 - 38 to the input 39 of the device provides - in registers 5 and 9. Privat each time

 „55

with managing high potential.

thirty

Further, with the following: the output of each pulse of the clock frequency is the following conditions:

E A L VL

E t A V I 2, 3,, i

D C, J

If the conditions are met, the values of E and B are written

the value of the counter is increased by one, which ensures that the values of the codes E and B | in the free parts of the registers.

which sets to single

state trigger 23 ;, signal

from which the element opens And 8,

five

0

the value of the first counter 15 is determined by the unit and via open: elements 4 and 8 in the first parts of registers 5 and 9, codes E and B, respectively, are recorded. If at least one of these conditions is not met; the counter value does not change and AND 4 and 8 remain closed. "Further, the clock signal delayed in the delay element 17 delays the code words in the i 3 and 195 registers, i.e. if words were written down before

E J oki, - 5-1 i V;, - С -;

THEN now there will remain f, E ;;,., B ,.

five

and (/) 3 С

WITH.

in registers 5 and 9. Privat every time

0

Further, with the following: the output of each pulse of the clock frequency is the following conditions:

E A L VL

E t A V I 2, 3,, i

D C, J

If the conditions are met, the values of E and B are written

the value of the counter is increased by one, which ensures that the values of the codes E and B | in the free parts of the registers.

51522232

As soon as the code of the last transit node B; viewed and moved out

register, its outputs will be, all and high potential from the output

ABOUT

of the OR-NO 14 element, the pulse shaper 20 will be triggered, the signal from which will reset the counter 15, register 1 and set the trigger 23 to the zero state, which will prevent the passage of the clock pulses to the comparison circuit 3 and the comparison block 22.

In addition, the signal from the output of the pulse generator 20 will allow decoding of the numbers of transit nodes recorded in register 9 and will start the distributor of 11 pulses. The decoder 10 determines the number of the message transmission direction by the switching node number.

-

On the outputs of the decoder 10, whose numbers correspond, the codes found are acceptable for transmission of transit data transmission network nodes, there are high potentials that prepare the corresponding elements AND 12 for opening. The distributor P pulses outputs one of its outputs, numbers which correspond to the numbers of the outputs of the high-potential decoder, the signal which opens the element AND 12 of the chosen direction of transmission of the message.

Cooperatively from the information input 40 of the device through an open signal from the trigger element AND 32 and element OR 26 enters the inputs of the group of elements AND 12 and through one (open) of them is output to the selected direction of transmission of output 41. At the same time, the counter 25 counts up. the number of characters in the message. As soon as it counts to the K-th value (starting with the next digit number, the code of the number A passed by the communication network switching nodes is transmitted in the message header) by the signal from the first output of the counter 25, the trigger 30 is set to O, As a result, And 32 will close and elements 31 and 21 will open. This prepares an entry in the header of the message sent to the selected direction of the new code value (E number) passed by the switching nodes. The recording is as follows.

6

ten

20

25

. | 5

m and

In accordance with the signals at the output of the distributor 11, the encoder 34 determines the number of the switching node that is selected for the subsequent transmission of the message. This number is compared on AND 32 elements with the numbers of previously selected nodes. A high potential appears at the output of one of the elements AND 33. In this case, the number of this block corresponds to the place of recording the number of the switching node selected for transfer to register 9 and the place of recording the new value of the total code of passed nodes by this message, which corresponds to the transfer to the selected node. We take this as an example.

Let, as a result of the device operation, codes of nodes 3, 5, 8, and 9 are written in register 9, and register 5 contains the corresponding summary codes of passed nodes ALZ; AL5 | AA8; AL9, and the distributor i1 selected node No. 8 for further transfer. a high potential appears at the output of the third element And 33 of the third group, which ensures reading through the second group of elements And 6 the value 30 of the total code of the passed nodes AL I A 8.

The summary code of the passed nodes is written to the message header through the element. OR 7 and the open element AND 31 .-, jr The reading of the code from register 5 is provided by pulses from the generator 29 through the open. element 21, in which case the frequency divider 24 ensures that the read speed from register 40 5 is matched with the transmission speed of information in the chosen direction for the transmission of a message.

After the entire code is written into the message header, the number of characters counter 25 45 gives a high potential on the second output, which sets the trigger 30 to the one state, as a result of which a VII is created to continue issuing the message, 50 zeroes the counter 25 and after delay element 18 zero registers 5 and 9.

After that, the device is ready to start servicing the next message.

55 Distributor 1I impulses for the jaeT selection of one of the found, acceptable transmission directions. This is done as follows (FIG. 2), To the inputs of the distributor.

the numbers of which correspond to the numbers of directions of communication allowed for the transmission of this message, high potentials are received, which prepare the corresponding elements AND 45 for opening. At the same time, the signal from the control input of the distributor trigger 47 is set to one and opens element AND 44. Pulses from the generator 43 through the element 44 and promote 1 on the register 42, while the outputs of the latter are connected to the second inputs of the elements 45, Pr the first coincidence of two units at the circuit inputs with a signal from its output through the element IL And 46, trigger 47 is set to O, and unit advancement through register 42 is stopped. The signal from the output of the element And 45 is

with allowing to send a message in this direction.

In the subsequent cycle, the operation of the circuit is repeated.

In this case, offset 1 in register 42 starts from the point where it stopped in the previous cycle. Such a solution allows the distribution of messages to different allowed directions even if the same statically transmission routes are used for several messages. This makes it possible to distribute the data flow of the data transmission network, excluding un-: justified overloading of individual directions (switching nodes) of the network.

Primer p. The message, transmitted from the sender to the recipient, passed the switching nodes with numbers 2 and 5 and got to the viewer - node with number 8.

At node number 8, switching nodes with numbers 2, 3, 6 can be used to issue this message. Suppose that the number of messages in the input buffers of these nodes is less than the allowable values. The table of conversion of node numbers into disjunctive codes is as follows.

In this case, the message arrives at node 8 with a header in which the number A is recorded - 0010010010.

As a result, addition in sum 2 is obtained:

E, A 2 0010010010;

A L A 3 0010010110;

0

50

Q

five

five

E.J AL 6 00101 10010, since E, A, E t A, and E i A, then in register 5, E, E, and in register 9 3, 6.

Assume that the pulse distributor 11 indicates the switching node number 3 for further transmission, in which case the message is sent to the corresponding direction of transmission to this node and the E code is written in its header. On subsequent switching nodes, the procedure is repeated.

Claims (1)

Formula invented and A device for switching messages in data transmission networks, containing first to fifth registers (bitmap, comparison circuit, first. And second AND elements, OR-NOT element, first delay element, comparison unit, pulse driver, first decoder , distributor pulses, the first group of elements And, the generator of clock pulses, moreover (the first, second, third and fourth control inputs of the device are connected to the information inputs of the first third and fourth registers, respectively, the outputs of elements And of the first group are The output of the device, the pulse driver output is connected to the reset input from the first register, to the resolution enable input of the first decoder and the pulse distributor start input, the output of the first delay element is connected to the shift offset of the second and third registers, the output of the first register is connected to the first input of the comparison circuit the output of which is connected to the first inputs of the first and second elements AND, the first information output of the second register connects to the second input of the second element AND, the outputs of the second register are connected at once The element is connected to the input of the pulse generator, the outputs of the third and fourth registers are connected respectively to the first and second inputs of the comparison unit, the output of which is connected to the third inputs of the first and second elements, And the output of the second element, And connected to the first input p of the register, the outputs of which are connected to the information inputs of the first decoder, the output of which connected to the inputs of the number of permissible directions of the pulse distributor and to the first inputs of the AND elements of the first group, the outputs of the pulse distributor are connected to the second inputs of the AND elements of the first group, characterized in that, in order to increase the throughput by reducing the amount of transmitted service information, rummatrr, sixth register, second and third groups of elements AND, encoder, first and second elements OR, third to sixth elements AND, first and second counters, second decoder, second element t delay, frequency divider, first and second triggers, the outputs of the first and second registers are connected respectively to the first and second inputs of the adder, the output of which is connected to the second input of the comparison circuit and to the second input of the first element And, the output of the comparison circuit is connected to the counter input of the first counter, the output of the comparison unit is connected to the information input of the first counter, the output of the pulse former is connected to the reset input of the first trigger, the reset input of the first counter whose outputs are not connected with the ion inputs are the second of the decoder, the outputs of which are connected to the second information inputs of the fifth and sixth registers, the output of the first element I is connected to the first information input of the sixth register, the outputs of which are connected to the first inputs of the corresponding elements of the second group with the output of the third element And, the reset inputs of the fifth and sixth registers are connected to the output of the second delay element, the outputs of the fifth register Disjunctive code oh oh About About About About About About 1 ABOUT oh oh oh oh oh 1 oh oh oh oh oh oh 1 oh .0 oh oh oh oh oh Ltd oh oh oh oh 1 oh oh oh oh oh oh 1 oh oh oh oh ten 15 ь 20 (25 Q. „ 35 40 connected to the first inputs of the corresponding elements AND of the third group, the outputs of the pulse distributor are connected to the corresponding inputs of the encoder, the outputs of which are connected to the second inputs of the elements AND the third group, the outputs of which are connected to the second inputs of the corresponding elements AND the second group, the outputs are connected to the inputs the first element OR, the output of which is connected to the first input of the fifth element AND, the device start input is connected to the installation input of the first trigger whose output is connected to the first input ( the fourth And element, the output of which is connected to the input of the first delay element and to the strobe inputs of the block and comparison circuit, the output of the clock generator is connected to the second input of the fourth And element and through the frequency divider to the first input of the third edenent And, the information input of the device is connected with the first input of the sixth element And, the inverse output of the second trigger is connected to the second input of the sixth element And, the output of which is connected to the first input of the second element OR, the direct output of the second is connected to the second by moves of the third and fifth elements And, the output of which is connected to the BTopo jy input of the second element OR, the output of which is connected to the counting input of the second counter and with the third input-, many elements of AND of the first group, the overflow output of the second counter , the overflow output of the second counter is connected to the single input of the second trigger, to the reset input of the second counter and the input of the second element, a delay. oh oh oh oh 1 oh oh oh oh oh oh 1 oh oh oh oh about about about 1 oh oh oh oh oh about about 1 oh oh oh oh oh about oh oh oh oh oh one oo about about about about about about about Q Thebes. i i L f f45 one 3 four :(