SU1453416A1 - Device for converting codes from language to language - Google Patents

Abstract

The invention relates to computing and can be used to create high-speed operating systems for information processing in systems with interactive mode of operation, debugging and execution of programs in hardware converters (emulators, interpreters ji ToP) with the direct implementation of

Description

one

The invention relates to computing and can be used to create high-speed operative information processing systems in systems with dialog operation, debugging, and executing programs in hardware converters (emulators, interpreters, etc.) with the direct implementation of high-level languages. level, as well as in devices with adaptive distributed information processing of povipennoy reliability.

The purpose of the invention is to increase the relationship and enhance the functionality by introducing adaptive distributed information processing.

FIG. Figures 1 and 2 show the functional diagrams of the device and the address modification block, respectively ;; in fig. 3 - time diagrams of the device; in fig. 4 shows an example of converting a high-level input language into an output language sequence of object codes; in fig. 5-7 - block diagrams of the conversion algorithm (codes of the output words are shown in hexadecimal form),

The device contains (Fig. 1) memory block 1, memory blocks, address register 3, synchronization block 4, address multiplexer 5, address modification block 6, trigger 7, clock generator 8, elements 9, 10, 11, - 11 Delays, information), dionic input 12, registers 13, -13 ,, addresses, input 14 of the input language conversion conditions, outputs 15i-15, registers 16, -16 steps, start input 17, reset input 18, address multiplexers, nodes 20, -20 translate intermediate language codes to output, address modification blocks, inputs 22, -22 intermediate language conversion conditions.

Blocks 6 and contain (FIG. 2) a register 23 and a bitwise adder 24 modulo two.

The address register 3 is intended for the temporary recording of the address of the next intermediate language word and information about the status of the nodes 20 of the conversion of codes from the intermediate language into the output language.

The address register 3 is divided into zones (FIG. 1): R, is the address zone of the next word of the intermediate language; R2.1 - R 2.P - parts of the zone of information about the status of nodes 20 of the conversion of codes from intermediate language into output, respectively. The output of the address register 3 generates the address decoded in the memory block 1.

The memory unit 1 is intended for storing intermediate language output words and information about the address of the next intermediate language word, as well as for storing information on the coordination of the operation of code points from the intermediate language into the output language.

Memory block 1 is divided into a number of memory fields, each of which has its own outputs (Fig. 1): P1 -, the control1 field of the multiplexer 5 addresses; P2O1-P2.p - floor coordinator. of the operation of the intermediate language code into the output language, respectively; ПЗ - intermediate word field; P4 - Address field for checking intermediate language translation conditions; A5 is a field of unmodified addresses of the next word of the intermediate language.

The multiplexer 5 is the pre-address address of the code 20 node from the intermediate language to the output language.

Memory block 2 is divided into a number of memory fields, each of which has its own output groups of memory block 2 (Fig. 1): P1 - switch address control field of node 10 address converting codes from intermediate language to output; P2 is a field of information about the status of the code conversion node from the intermediate language into the output language: PZ is the word field of the output 15th language; Q4 is the address field for checking the conditions of the output language conversion; A5 - field of unmodifiable addresses of the next word of the output language. The address multiplexer 19 is designed to form the R1 zone of the address register 13 depending on the information recorded in the P1 field of the memory block 2.

If the corresponding field P1 is peppered to form the R1 zone of register 3 of the address c. Depending on the informational information output of the 2 nd block recorded in the P1 field of the memory 1 block, the value is Log.1, thio multi

If the corresponding field P1 is the first information output of the block 1, the address piplexer 19 switches to the reception of the next intermediate language word from the output of the block 1 of the memory.

m t has a value Log ... G, .to a multitude, but if the given output has a value

Log.O, the address multiplexer .19 switches to receiving the next address of the next word of the output language, received from the output of the address modification block 21 and the fifth output of the memory block 2 corresponding to the PZ field of the block 2,

Tiplexer 5 switches to receive. next input word from input 12 of the device, and if this output is Log.O, the address switch switches to receiving the next address of the next intermediate language word from the output of block 6 of the modification of the address of the fifth output of memory 1 corresponding to the field A5 of the block 1 memory.

The address register 13 is intended for dp of temporarily recording the address of the next word of the output language (ipi the starting address of the output sequence) and information on coordinating the operation of the code conversion unit from the intermediate language to the output one.

Address register 13 is divided into zones (Fig. 1): R1 is the address zone of the next word of the output language; R2 is the information area for coordinating the operation of the code conversion unit from the intermediate language to the output.

The output of the register 13 forms the address decrypted in memory block 2.

The memory unit 2 is intended to store the output language words and information about the address of the next word, as well as to store information about

the state of the node 20 for converting codes from the intermediate language into the output language.

Memory block 2 is divided into a number of memory fields, each of which has its own output groups of memory block 2 (Fig. 1): P1 - switch control field of the address of the code conversion node from the intermediate language to the output; P2 is a field of information on the status of the code conversion node from the intermediate language into the output language: PZ is the word field of the output language; Q4 is the address field for checking the conditions of the output language conversion; P5 - field of unmodified addresses of the next word of the output language. The address multiplexer 19 is designed to form the R1 zone of the address register 13, depending on the information recorded in the P1 field of the memory block 2.

If the first information output of memory block 2 corresponding to the P1 field is set to Log.1, the multi-

the second information output of memory block 2 is set to Log.1, the multi-

The address type 19 switches to the reception of the next intermediate language word from the output of memory block 1.

and if the given exit has a meaning

Log.O, the address multiplexer .19 switches to receiving the next address of the next word of the output language, received from the output of the address modification block 21 and the fifth output of the memory block 2 corresponding to the PZ field of the block 2,

Block 6 address modification pred. assigned to form an added address of the next address word, as well as to direct the conversion process along one of the possible paths determined by the relevant external conditions.

Address modification blocks 21 have a similar purpose and are different, for example, in size.

The device works as follows

At the initial moment of time, the memory elements of the device may be in an arbitrary state. The generator 8 tactical pulses at the nominal power is always in operation and gives a sequence of clock pulses according to the timing diagram (Fig. 3).

The device is reset to its initial state upon arrival at the input.

18 signal Reset, which sets trigger 7 to the zero state. The signal from the inverted output of the trigger 7 is fed to the reset inputs of the address 3 register and the address registers 13 and produces them reset. Thus, the address input of memory block 1, as well as the address inputs of all memory blocks 2 of the intermediate language code conversion node 20, receives from the respective registers the zero address of the sync signal input to the synchronization input of memory 1 of the delay element 10, is performed d, - Shifrash1 zero address in memory block 1, and on the sync signals received at the inputs of blocks 2 memory nodes

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For the corresponding r, clock sync impulse from the generator output 8 clock pulses to the address register 3 is written 5 from the output of the multiplexer 5 res the initial address converts the input language to an intermediate one, according to the corresponding clock pulse from the group of outputs of the generator 8 to the hirs 13 the output is recorded from the inputs of the multiplexers 19, the address responsible for the initial addresses n 15 of the formation of codes from the intermediate language into the output. On the initial and the conversion itself, in the field P1 of the memory block and the fields x P1 of the blocks 2 of the memory, single information is recorded,

ТЧЯС TTfii-ij h .- .. l ..

  wjxuo and. memory nodes

/ s convert intermediate zyrn "-j- -, to

From the group of outputs of the generator 8, the same impulses are produced, and if it is produced,. enters the zero address qi in blocks 2 of the memory of all nodes 20 of the intermediate language conversion.

At the zero address in fields P4, P5 of memory block 1 and fields PA, P5 of all memory blocks 2, some initial conversion addresses are recorded, which go to the corresponding registers 3 and 13 addresses, but are not recorded in them by the arrival of clock signals, These registers are set to zero. In all other fields of all memory blocks, zero information is recorded at the zero address. Thus, the address inputs of the blocks 1 and the memory still receive the zero address, and then the device is next - it generates the zero address until WilT T TTTTnj- T 7 ... - fj 1 (2i iiup,

trigger 7 will not be translated to a single state. When the signal is reset from input 22 of the device. Reset, the device will remain at the end of the TTTOK. I-r ttr-r

nominal state before the zero state is maintained. T G °° P ™ The operation of the nodes 2 states of the trigger 7. "At the first 45 conversion codes with intermediate

NPGT OOLiT / - l T-, i ..

-.j. iiaci Hcl

The control inputs are, respectively, multiplexers 5 and and switches them to receive words, respectively, input and intermediate. For all the remaining fields of all memory blocks, zero information is recorded at the starting address. in ni "° of single information from the floor - P1 of the memory block 1 from the input 12 of the device enters the input word which through the multiplexer 5 address enters the input of the register 3 of the res and via the corresponding synchronous 35 pulse from the output of the generator 8 enters the register 3 addresses. On the corresponding sync pulse arriving at the input of block 1 of the memory from the output of the delay element 10, Aor 40 consequently, the first word of the intermediate language is written in the PZ field of the block 1 of memory.

At the same time, in the fields P2.1-P2.p of the memory block 1, the infogazhi is formed to coordinate the work of the nodes 20

TTTL oRn i3f5j - ,, .. ™. -.

on the weekend. Each word in the input language corresponds to either one word of the intermediate language (we press One to One), or a sequence of words of the intermediate language (One to several mode).

The operation of the device begins at the input 17 of the signal device. The absence of the signal at the input 18 of the signal

 . This signal sets the trigger 7 to one state synchronously with the arrival at the clock input of the trigger 7 of the corresponding sync pulse from the generator output 8 clock pulses (Fig. 3). The output of the trigger 7 removes the reset from the register 3 addresses and all registers 13 addresses.

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For the corresponding r, the clock pulse from the generator output 8 clock pulses into the address register 3 is written from the output of the multiplexer 5 address, the starting address for converting the input language to the intermediate one, and for the corresponding clock pulses from the output group of the generator 8 to the registers 13 for the code conversion node nodes from the intermediate A language in the output is recorded from the outputs of the multiplexers 19, the addresses corresponding to the initial addresses of the conversion of the codes from the intermediate language to the output. At the initial addresses of the conversion, in field P1 of memory block 1 and fields X P1 of memory block 2, a single information is recorded that TTHYa TTfii-ij h.- .. l.

n "-j- -., to

R T °° which vkody,. arrives at

R T °° which vkody,. arrives at

. T ° ° P ™ Works of nodes 2 5 code conversion with intermediate

-.j. iiaci Hcl

Controlling the inputs of multiplexers 5, respectively, and and switches them to receive words of the input and intermediate, respectively. In all other fields of all memory blocks, zero information is recorded at the starting address. in ni "° of single information from the field P1 of the block 1 of the memory from the input 12 of the device enters the word of the input language. which, through the multiplexer 5 of the address, enters the input of the register 3 of the address and according to the corresponding synchronous 5 pulse from the output of the generator 8 is entered into the register of the 3 addresses. Thereby, the first word of the intermediate language in the PZ field of the memory 1 block is generated by the corresponding sync pulse arriving at the input of block 1 of memory and from the output of delay element 10.

At the same time, in the fields P2.1-P2. Of the memory block 1, the infogaming is formed to coordinate the work of the nodes 20

TTTL oRn i3f5j - ,, .. ™. -.

.. T ° ° P P Works of nodes 2 45 conversion codes with intermediate

NPGT OOLiT / - l T-, i ..

50

on the weekend. Each word in the input language corresponds to either one word of the intermediate language (the One to One mode), or a sequence. the complexity of the words of the intermediate language (mode One to several).

With the implementation of the regime. One at a time with the word of the intermediate 65 language, a single information from the P1 field of the memory unit 1 is delivered, and the address multiplexer 5 switches to receive the next word of the input language.

7145

With the implementation of the One-to-several mode, each intermediate word of the intermediate language can be either the output word of the linearity of the words, or its address depends on certain conditions determining the process of converting the input language into the intermediate language. The next unmodifiable address is generated in the P5 field of memory block 1 and is sent to the address multiplexer 5. The address for checking the conversion conditions is formed in the P4 field of the memory unit 1 and modified by some external conditions in the unit 6 by modifying the address, after which it also goes to the address multiplexer 5, where the address of the next intermediate language word is generated, which is received through the address multiplexer 5 The inputs of the register are 3 addresses. In addition, the address of the next word of the intermediate language depends on internal conditions.

nodes 20, -20 "translate codes from intermediate language into output, information about which is fed to the inputs of zones R2.2-R2.n of register 3 addresses directly.

The intermediate language word from the field output of the PZ of the memory block 1 is fed through the address multiplexers 19 to the inputs of the R1 zones of the registers 13 to the corresponding nodes of the code conversion 20 from the intermediate to the output languages. In addition, the inputs of the R2 zones of the address registers 13 come from fields A2.1 to A2, n of the memory block 1, information on coordinating the work of nodes 20 converting codes from an intermediate language into an output and thus form addresses of the words of the output languages, which the corresponding sync pulses from the output group of the generator 8 are recorded in the address registers 13, and sync pulses from the outputs of the delay elements 11 of the code conversion nodes from the intermediate language to the output are decoded in memory blocks 2,

Each word of the intermediate language corresponds to either one word of the output language (One to One mode), or a sequence of words of the output language (One to several mode

to).

When the One mode water mode is implemented, at the same time as the output language, a single information is output from the P1 floor of the memory block 2, and the address multiplexer 19 switches to receive the next intermediate language word.

When implementing the One into several mode, each successive word of the output language can be either the output word of a linear sequence of words, or its address depends on some conditions determining the process of converting the intermediate language to the output. Another unmodified address is generated in the P5 field of the memory block 2 and goes to the address multiplexer 19. The address for checking the conversion conditions is generated in the P4 field of the memory block 2 and modified by some external conditions in the address modification block 21, after which it also goes to the address multiplexer 19, where the address of the next word of the output language is formed, which through the multiplexer 19 of the address goes to the inputs of the register 13 addresses. In addition, the address of the next word of the output language depends on the information on the coordination of work for each of the nodes 20, -20 „translate codes from intermediate language into output, which goes to the inputs of zone R2 of the registers 13 addresses of each of the nodes 20 convert codes from intermediate language to output from the outputs of fields P2.1-P2.P of memory block 1.

The words of the output language from the outputs of the PZ fields of the memory blocks 2 are fed to the inputs of the registers 16 and, through the corresponding synchroshulses from the outputs of the delay elements 11, are locked in them, after which they go to the outputs 15 of the device.

Blocks 6 and 21 of the address modification are analogous in implementation and may differ in size. Block address modification works as follows.

Input 14 (22) is supplied with a parallel code of input conditions and is stored in a register on a synchronization pulse, through a register (if there is a unit in the first position of the first group supplied to the input and input of the register 23), it is fed to the one-digit adder 24 modulo two. At the same time, the parallel code of input conditions is fed to the second input of bitwise adder 24. To the third input of bitwise adder 24 is supplied9. 14534, the address of checking the conditions of the conversion from the first group of inputs of the block 21 of modifications. The work of the one-bit adder is described by the following equation:

15

20

25

thirty

(A1 YBi) ci Di

The equation describes operations on the 1st bit of the input words, and

I i

AI is the 1st bit of a word, xp is incorrect in the register .23; c - the 1st bit of the word input conditions, fed directly to the adder 24; C1 is the 1st bit address of the conversion condition check; DI is the 1st bit of the output word of block 6 (21) address modification; Y - operations Logical © - operations Addition modulo,

Thus, block 6 (21) of the address modification implements the function of address modification both depending on the content of the word’s output tekup word and the content of the word of the input condition previously submitted at an arbitrary time, fixed by the corresponding command in the registrar 23.

Consider an example of the operation of a device when converting a high-level input language into intermediate type assembly language and object code language. I.

In this example, the following is: ovo input

The High Level language is transformed into a three-word sequence. intermediate language, then each of the intermediate language words is transformed in turn in accordance with the sequence of two words of the output language of the object codes (Fig. 4). In this case, the proposed algorithm is implemented by a device containing 45 transform nodes 20 codes from intermediate zypsa to output. On codes of two nodes 20, for example, the first and the third, form: - Coziness of the word of an equivalent sequence in the language of the object and 1x codes,. and at the output of, for example, the second node 28, an equivalent intermediate word sequence is formed. The transformation is carried out in accordance with the block diagram of the transformation algorithm for a given rimer, which contains a consistent sequence of address words, taking into account

35

50

55

ten

6

zones of the address registers and codes, contents in the corresponding address words of the memory cells, taking into account the fields of the memory blocks, as well as taking into account the information and links of the device (Fig. 5-7).

15

20

25

thirty

Yu

0 5

five

0

five

Claims (1)

1. A device for converting from one link to another, containing a memory block, an address register, an address multiplexer, an address modification block, an intermediate intermediate code to an output code conversion node, and a synchronization block, the first information input of the address multiplexer, is connected to the information input of the device, the output of the multiplexer, the address is connected to the first information {{acioE} input of the address register, the output of which is connected to the address input of the memory unit, the first output of which is connected to the first input of the modi ation addresses, a second input coupled to the input conditions of the tongue converting the input, the output bit d.y ad.resa modification unit and second output unit connected to the memory of the second information bits of the input address multiplexer, the third output the memory unit is connected to the first information input of the first intermediate language code conversion node, the output of which is connected to the first information output E of the device, the device start input is connected to the synchronous input of the same name, the first, second, third and fourth outputs of which are connected to the gating inputs the address register, the memory block and the first and second gates of the first intermediate language code conversion node, characterized in that 5 in order to increase the speed Corollary rasschire- and audio functionality by introducing an adaptive distributed information processing, it entered from the second to n-th conversion codes zy- intermediate nodes. 1k to the output, the outputs of which are connected from the second to the nth information outputs of the device, respectively, the first information inputs and the first inputs from the second 2 Work tact Tact rvdoty 1 ycmpoucmSa Stlbbo $ one language TiocJKSo arr№j Mxmb intermediate language script Sequence sequences with / bypass language FIG. H F RV Q 0 Q 0 0 0 Q 1 0 0 0 0 PZ 000000 Ofrtjj n ОГо и тик, QOO o bQ Q Q О О О Q yt So that one g 3 " five Sign in I Ri i 0 0 0 0 00 00 00 Sh, in Q Q Q I 00 0 1 00 Kl Q Q Q Q Q о о 0 7x1 О О ОГГГОО О О О О О О О О pch A5 / 7g; / 72 ff23 About Q Q About About About L-A K O 1 L A K 1 00000 000000 000000 About About About 1 About Q About 1 About About About Oh oh Q 1 about j About 1 About About About About 00 00 or 00 00 00 J l 1 M5 I V & Vod