SU1451857A1 - A-d converter - Google Patents

Abstract

The invention relates to information-measuring and computing technology and can be used in systems of automatic control and management of technological processes. The invention allows for improved conversion accuracy by adaptation. This is achieved by the fact that an analog-to-digital converter containing a reference element, a clock generator, an AND element, a shift register, triggers, AND elements, comparison elements, frequency dividers, valve elements, a constant voltage source, keys, a counter, and delays, subtraction unit, analog adders, adder, “nvertor, elements OR. 3 il.

Description

|| nd

SP

OQ SP

The invention relates to information-measuring and computing technology and can be used in systems of automatic control and management of technological processes.

The aim of the invention is to improve the accuracy of conversion by adaptation.

FIG. 1 shows a functional diagram of the converter; figure 2 shows the analog-to-digital conversion of the input signal.

The analog-to-digital converter contains a bus 1 of installation in O, the element OR 2, the trigger 3, the key 4, the element OR 5, the analog adder 6, the element 7 of comparison, the element AND 8, the keys 9, 10, the element OR 11, the trigger 12, the element 13 delays, subtraction unit 14, valve elements 15, 16, inverter 17, element OR 18, element OR 19, analog adder 20, element 2 of comparison, element AND 22, key 23, element OR 24, element 25 of comparison, source 26 constant of these voltages, the element 27 comparison, the element And 28, the element And 29, the element 30 zadorki, the element 31 of the delay, the element And 32, the element And 33, the element 34 comparisons, element-35 comparisons, an element OR 36, a trigger 37, an element AND 38, a trigger 39, an element NOT 40, an element NOT 41, an element And 42, a clock oscillator 43, an element And 44, an element And 45, a divider 46 frequency, input bus 47, element And 48, element And 49 ,. AND 50, shift register 51, adder 52, output buses 53, 54, AND 55, frequency divider 56, OR 57 J element And 58, counter 59, OR 60 element, input bus 61, OR 62 element, element OR 63, element AND 64.

The Converter operates as follows.

At the moment of time, a single pulse is applied to bus 1, which sets the triggers 3, 12, 37, 39, analog adders 6, 20, dividers 46, 56, register 51 and adder 52, to the zero state, and counter 59 to the unit state .

At the second output of the source 26, the voltage is set to a voltage equal to -id / 2, on the first - Id / 2, on the fourth - id, and on the third - 1.5 Id, where Id is the step

discretization of the voltage. The converter is ready for conversion (signal to digital code,

At, time t ,. The input bus 47 receives a signal of arbitrary shape (Fig. 2), which is fed to the first inputs of the elements 27, 34, 35 of the comparison and the subtractor 14, to the second input of which the same signal is fed, but delayed by the elements 13 for a time, where TD is the sampling rate

The second input of the element 34 receives a voltage equal to 1 d / 2, from the first output of the source 26, and its second output to the second input of the element 35 receives a voltage equal to -id / 2. When the magnitude of the voltage of the signal being converted is Ugj, the absolute value will become greater, i.e. then at the output, elements 34, 35, according to Vits, the voltage is a logical unit depending on whether it is positive or negative. The voltage of the logical unit through element 36 puts the trigger 37 in the one-unit state.

The voltage of the logical unit from the inverse output of the trigger 37 is supplied to the second inputs of the elements 32, 44, allowing the passage of information supplied to their first inputs to and from

OUTPUTS.

Clock pulses from the output of the clock generator 43 through the element 44 is fed to the first inputs of the elements 38, 45,

The first clock pulse arriving at the first input of element 38 arrives at its output, since at its second input there is a voltage of a logical unit from the direct output of flip-flop 39, and translates flip-flop 39 into a single state. The pulse from the output of the element 38 through the elements 33 and 32, respectively, is supplied to the second and first inputs of the elements 24, 28.

Depending on which of the voltages arriving at this time point to the first and second inputs of element 27, is greater, i.e. as the shape of the signal being transformed, the first or second of its output will contain the voltage of a logical unit that goes to the first or second input of elements 29 and 28, respectively. At the output of element 29 or 28, a clock pulse appears, which arrives at the first inputs of the key 4 or 10, respectively, opening the corresponding one from the switch, and triggers trigger 3 or 12 into a single state.

The voltage from the output of block 14 goes to the inputs of elements 15, 16. If the voltage is positive, then it goes through the element 15 (element 16 does not pass it) to the second input of element 18 and then to its output, and if negative, then through element 16 (through element 15 does not pass) it goes to the first input of element 18 and then to its output, previously inverted by inverter 17.

Thus, the output of element 18 will be a positive voltage equal to l4a (t) / Ujt) -Ujt-rA) J, where UgK is the input voltage; Ug (t-) is the input voltage delayed by the sampling interval.

The voltage (t) arrives at the second inputs of the keys 4 and 3. For a time equal to the duration of the clock pulse, the instantaneous value of the voltage received at the second inputs of the key 4 or 10 at a given time arrives at the output of the key 4 or 10 and further, the input to the first or second summing input of the analog adder 20 or 6, respectively, is written into it.

The first clock pulse is also supplied through the element 63 to the inputs of the elements 30, 31.

The delayed pulse from the output of the element 31 appears after time 1 / 3T from the moment it arrives at the input, since the delay time of element 31 is 1 / 3TTI, where IV is the period of the following clock pulses and enters the elements 48, 49, 50, allowing The arrangement of the first triad in the register 51 and the numerical value of the sequence of the signal being converted and the output of the adder 52.

The output states of the elements 25, 7, 2 are recorded in the first, second, and third bits of the register 51, respectively, and the states of the elements 7 and 21 are entered, respectively. summing and subtracting the inputs of the adder 52, changing, respectively, its state.

If U6, /Uв, (t)-U., (t-gd) ./2 or I70, / UJt) -U „(t-gd) / id / 2, then respectively in the second or third section The first triad in register 51 is written O.

1, otherwise 0

If life, 1.5U or 2 (7, at the output of element 25 is a voltage of 0 logical zero and the first bit of the first triad, the first bit of register 51, respectively, is 0, otherwise it is 1.

If Ufi and d / 2, then one is added to the content 5 of adder 52, since the voltage of the logical unit is applied to its summing input.

If, d / 2, then one is subtracted from the content 0 of the adder 52, since the voltage of the logical unit is applied to its subtracting input.

The content of the adder 52 comes from its output on the output busbar 54. 5

The pulse from the output of the element 30, delayed by the time 2 / ZT from the moment. its arrival at the input, since the delay time of element 30 is 2 / ЗТ, 0 where the period of the clock of the clock generator 43 follows the first inputs of elements 8 and 22. Depending on which of the triggers (3 or 12) is in a single state, a single pulse appears at the outputs of element 8 or 22.

A single impulse from the output of element 8 or 22, respectively, is fed to the second inputs of key 9 or 23, respectively, and the voltage from the output goes to the subtractive output of analog adders 6 or 20 and subtracted from the content g of the MO of the corresponding adder.

The output voltage of the corresponding analog adder 6 or 20 will become equal and fUaK (t) -Ugj (t-Cd) / - Id

or u, „/ u ,, (t) -u„ (t-d) -ud.

Second clock pulse output

element 44 is fed to the first inputs of elements 39 and 45. At the second input of element 38 there is a logic zero voltage from the direct output g of flip-flop 39, and the second input of element 45 is the voltage of a logical unit from its inverse output, so it passes - output of element 45 only,

The clock pulse from the output of the element And 45 enters the counting input of the divider 46 and the elements 55, 58,

Since the state of the counter 59 is single, then the output of the element 57 causes a voltage of the logical unit that goes to the second input of the element 55, allowing the clock pulse to pass to its output, from which the clock pulse goes to the counting input of the divider 56, the shift input of the register 51, the shift information in it for one bit, and the output bus 61, On the output bus 53 appears the first bit of the first triad, and on the output bus 61 - a clock pulse corresponding to the first bit the first triad.

If at the output of element 25 there is a voltage of a logical unit, i.e. when the voltage at the first input is smaller than 1.5id, the clock pulse passes through element 58 to the counting input of counter 59, subtracting one from its content.

The third clock pulse from the output of the element 44, having passed through the element 45, enters the counting input of the divider 46 and the elements 55, 58,

The voltage of the logical unit from the output of the element 57 goes to the elements 55, Sv, From the output of the element 55, the clock pulse goes to the input of the divider 56, to the shift input of the register 51, the information in it is one bit, and to the output bus 61.

On the output bus 53 will be the second bit of the first triad, and on the output bus 61 - the second clock pulse corresponding to the second bit of the first triad,

 The third clock pulse enters through the element 58 to the counting input of the counter 59, subtracting from its contents a unit, t, e. its contents will be equal to one,

The fourth clock pulse from the output of the element 44 through the element I 45. The divider 46 enters the counting input and the elements 55, 58 .. Since the counter 59 contains one, then its first output contains the voltage of the logical unit that arrives at the output of the element 57, at the output of the element 55 a pulse appears, which pic blunt on the counting input of the divider 56, to the shift input

five

register 51, the shift information in it for one bit, and the output bus 61.

On the output bus 53, the third discharge of the first triad appears, and on the output bus 61 - a clock pulse corresponding to the 1st third discharge of the triad,

Since divider 56 has a division factor of three, a single impulse appears on its output, which is (- s) arrives at the first input of AND 64. If u4: id / 2 and then, the output of element 62 is the logical zero voltage which arrives at the second input of the element And 64, and the impulse received at its first input does not pass to the output.

If ib, is 11d / 2 or, then the pulse passes to the output of the element 64, since the voltage of the logical unit is present at its second input. But in this case, Ug- | Ug (t) - -HB, (t-C-d) f 1, 5U or U,; o, (U6, (t) - ti, (tt.) / 1,5U. and when passing

ol (C

They do not pass the previous three pulses to the output of element 58, since

at its third input there is a logical zero voltage, and the contents of counter 59 remain unchanged, i.e. is in a single state.

From the output of the element 64, a single pulse arrives at the inputs of the elements 30, 31.

From the output of the element 31, the delayed pulse arrives at the elements 48, 49,

50 in time 1 / ЗТу from the moment of its arrival on an input.

The corresponding bits of register 51 are recorded — the states of the elements 7, 21, 35. This will be

the second triad of signal conversion in register 51.

If the content of the analog adder is 6 or 20 greater than the voltage Ud / 2, then the output, respectively, of the element

7 or 21 is the voltage of the logical unit, and if it is greater than 1.5Pd, then the output of the element 25 is a voltage of logical zero, otherwise the outputs of the elements 7 and

21 - logical-zero voltage, and at the output of element 25 - logical unit.

The output state of the element 49 is fed to the summing input of the accumulator 52, and the state of the output of the element 50 is fed to the subtracting input of the adder 52

If the output of cell 49 or 50 is the voltage of a logical unit, then the state of adder 52 changes.

Through time 2/31, at the exit element

that 30 appears delayed by time. 2 / ST, the pulse that arrives at the first inputs of elements 8 and 22, the second inputs of which receive voltage from the inverse outputs of the flip-flops 3 and 12, respectively, depending on which of them is in the unit state. The voltage of a logical unit from its inverse output passes a delayed pulse, which arrived at the first input of element 8 or 22, respectively, at its output. This pulse opens, respectively, the key 9 or 23, the subtracting input of the corresponding analog adder 6 or 20 receives a voltage equal to Od, which is subtracted from the contents of the corresponding, analog adder 6 or 20

The next clock pulse from the output of element 44, passing through element 45, goes to the counting input of the divider 46 and to elements 55, 58. If the output of element 57 is a logical zero voltage, then the clock i pulse does not pass to the codes of elements 55, 58,

If the output of the element 25 was the voltage of logical zero, t, e. the voltage at its first input is greater than 1.5Ui before the second pulse arrives from the output of element 44, then the state of counter 59 remains single, since the first input of element 58 contained a logical zero voltage and no pulses at its output.

In this case, the converter operates according to the above described althorhythm, only the element 58 will not pass clock pulses to the counting input of the counter 59, When the output of the element 25 turns on the logical unit after the next reading from the content of the analog adder 6 or 20 voltage Ui, the next three clock pulses, having passed through element 58 to the adjacent input of counter 59, will set it to the zero state.

When the output pulse splitter 46 is a single pulse, it will be

518578

indicate the second sampling point, since С д п .Т, where

ten

20

15

,

n - the division factor of the divider 46, the period following the clock and

pulses. This impulse through elements 33 and 32 will go to elements 28 and 29,

Depending on the output of element 27, the voltage of the logical unit is present, a single impulse will pass through element 28 or 29 at its output. This single pulse will set (or leave in one state) trigger 3 or 12 and translate (or leave in zero state) trigger 12 or 3. A single pulse will also draw a key 4 or 10 for the duration of its duration. To the content of analog adder 6 or 20, respectively, summarizes the instantaneous value of the voltage difference at times corresponding to the second and first sampling points, i.e. U, g / U- (t + cd) - 25 -Ujt) /.

If before, at the first sampling point UgJ (t) -U (t-Г д) 0, and at the second sampling point U (t + t) - Ug (t) О, then in analog summer 30 it will be voltage equal in magnitude, (t + Gd) to Ug (t) /.

If lyt) -Ug (t-td) O, and iyt + + d) 0, then in analog adder 6 there will be a voltage equal in value to 35 U6 / Ujt + i) -U, (t) /.

If lyt) -Ug, () о and Ug () (t) 0, then ъ analogue adder 6 will be / voltage, equal in magnitude to U6- / UeJt + e -) - U (t) + U ", / y and if 40 b) -i, () O and Ujt + r) -Ue, (t) “p. Oh, in the analog adder 20 there will be a voltage equal in magnitude

hell.) () + u2o, /, where, /11, .Kid /, -id / 2 and id / 2-, and; 45, -id / 2 and о ,, where k is the number of amplitude discretization levels in a time discretization interval.

If idi, id / 2 or, then the output of element 7 or 21, respectively, is the voltage of the logical unit, otherwise, the voltage of the logical zero.

If and. 1, 5, or 5, then

50

55

at the output of element 25, the voltage is a logical zero, otherwise it is the voltage of a logical one.

A single impulse from the output of the divider 46 through the element 60 also enters the installation input. counter. 59, set it to a single state, and through element 63 to the inputs of elements 30 and 31. A single impulse delayed by element 31 enters elements 48, 49 and 50. Depending on the state of the outputs of elements 7, 21, 25 V Register 51 will form the next triad.

The output states of the elements 49, 50, respectively, are fed to the summing and subtracting inputs of the adder 52. Depending on the voltages applied to them, the state of the adder 52 changes. The contents of the adder 52 are fed to the output bus 54.

The delayed impulse from the output of element 30 is supplied to elements S and 22. When the first input of element 8 or 22 of a logic unit voltage is output, a delayed pulse appears from the contents

1/31. ,, will go to the elements 48,49, 50, allowing the census of the state of the outputs of elements 7, 21 and 25, respectively, 5 in the first, second and third bits of register 51. In register 51, the next triad will be formed

The output voltage of a logical zero or unit from the outputs of the element 10 49, 50 is applied respectively to the summing or subtracting input of the cum m-ator 52..

The content of the adder 52 is increased or decreased by unit 15, depending on which input a logical unit received. The contents of the adder 52 p steps on the output. Psnu 54.

Impulse from the output of the second element

20 30, delayed by 2/31

and

by

step on element B, 22. Depending on which of the triggers (3 or 12) is in a single state, the voltage

"-V W vy" i: iruri, ncnip / l ftcnilti JlUl ICHSSKOI

analog adder 6 or 20, respectively, 25 units with the inverse output of one

A voltage equal to ID is deducted.

The next clock pulse clock generator 43 through the elements 44, 45 is fed to the counting input of the divider 46 and the elements 55, 58.;

If the output of the comparison element 25 is a logical zero voltage, i.e. ib1,5id or, then impulse. passes, if, 5id or U, 2o 155id5 then this impulse does not pass to the output of element 58, since its first input voltage is a logical zero, and the state of counter 59 remains unchanged. Through element 55, the pulse arrives at the counting one. the input of the divider 56, the shift input of the register 51, the shift of its contents by one bit (at the same time the output

one of them passes a single delayed pulse to the output of element 8 or 22, respectively, and opens for the duration of the pulse

30 key 9 or 23 respectively. The voltage, equal to Id, from the output of the corresponding key 9 or 23 goes to the subtracting input, respectively, of analog adder 6 or 20. The content of adder 6 or 20 decreases by 11 and becomes 11) / - id or, (t + 4) ( t) / -id If and, 1,5id or and (gog, 1,5id, then at the exit

40 elements 25 - the voltage of the logic zero and the converter will work according to the described algorithm until the inequality 1b / u in (tg)) - u6, (t) / - ud 1,5id or

-Q -vts - / - tjx / - D - D

the skull .53 appears the contents of the first 45 gf, (+} -lUt l -k-U. 1.50. th razdada scittampy tpi PM). m on v-i -d

the raze of the triad to be matched), and on the output bus 61, you will see 1 that the first bus raises the triad ../

The second and third impulses perform the same actions as the previous one. The only difference is that after the third pulse at the output of the divider 56, according to the wits, there is a single pulse that goes to the inputs of the elements 30, 31, if there is a voltage of logical unit at the second input of the element 64.

The delayed pulse at the output of the element 31 Vits through time ,, equal to

where k-1,1. When these inequalities are fulfilled, the output of element 25 is the voltage of the logical unit, which is fed to the first input

50 ment .58, thereby permitting the passage of pulses to its output, which are delivered to its second input. After this, three pulses go to the subtracting input of counter 59 and its state 55 becomes zero. The logical zero voltage from its outputs is passed through element 57 ,. prohibits the passage of pulses through the elements of 5 58, and a single pulse from the output of de

45185710

1/31. ,, will go to elements 48.49, 50, permitting a census of the state of the outputs of elements 7, 21 and 25, respectively, in the first, second and third bits of register 51. In register 51, the next triad will be formed.

The output voltage of a logical zero or one from the outputs of elements 10 49, 50 is applied respectively to the summing or subtracting input of sum-ator 52..

The content of the adder 52 is increased or decreased by one in 15, depending on what input its logical unit voltage came from. The content of the adder 52 is fed to the output. Pshnu 54.

Impulse from the output of the second element

20 30, delayed by 2/31

and

enters elementy B, 22. Depending on which of the triggers (3 or 12) is in a single state, the voltage of the logical

"-V W vy" i: iruri, ncnip / l ftcnilti JlUl ICHSSKOI

25 units with one inverse output

25 units with one inverse output

one of them passes a single delayed pulse to the output of element 8 or 22, respectively, and opens for the duration of the pulse

30 key 9 or 23 respectively. The voltage, equal to Id, from the output of the corresponding key 9 or 23 goes to the subtracting input of the analog adder 6 or 20, respectively. The content of the adder 6 or 20 decreases by 11 and becomes 11) / - id or (t + 4) ( t) / -id If and, 1,5id or and (gog, 1,5id, then at the exit

40 elements 25 - the voltage of the logical zero and the transformer will work according to the described algorithm until the inequality 1Ü / Uв (t+гд )- U6, (t) /-k.Ud 1,5id or

 / - tjx / - D - D

45 gf, (+} -lUt l -k-U. 1.50. V-i -g

rc, (+} -lUt l -k-U. 1,50. v-i -g

where k is 1.1. When these inequalities are fulfilled, the output of element 25 is the voltage of a logic one that goes to the first input of element .58, thereby allowing the output of impulses to its second input. Thereafter, three pulses are fed to the subtracting input of counter 59 and its state becomes zero. The voltage of an ogonic zero from its outputs, passed through element 57 ,. prohibits the passage of pulses through the elements 55, 58, and a single impulse from the output of

Frequency 56 allows the formation of the last triad at the second sampling point, subtracting from the contents of the first 6 or second 20 analog adder the U value and finally forms the state of the adder 52 corresponding to the value of the amp voltage of the second sampling point.

Claims (1)

Invention Formula An analog-to-digital converter containing a first comparison element, the first input of which is an input bus, a clock generator, the output of which is connected to the first input of the first element AND, the shift register, four triggers, fourteen elements AND, characterized in that accuracy, five comparison elements, two frequency dividers, two valve elements, a source of constant voltages, four switches, a pulse counter, three delay elements, a subtraction unit, two analog adders, an adder, an inverter, two elements NOT, twelve elements OR, the first inputs of the first, second, third, fourth and fifth elements OR, the installation inputs in O of the first and second triggers, the first and second frequency dividers, the shift register and the adder are combined and are the setup bus zero, The second element OR is connected to the second input of the second element OR and connected to the output of the second element AND, the third input of the first OR element is combined with the installation input in 1 The Fourth flip-flop, a first the input of the first key, with the second input of the third element OR and connected to the output of the third element AND, the first input of which is combined with the input of the first element NOT and connected to the first output of the second comparison element, the second input of the third element AND combined with the first inputs of the second and fourth elements AND and connected to the output of the pth element And, the first the input of which is connected to the output of the sixth OR element, the second input is combined with the second input of the first one AND, and is connected to the inverse output 12 the second trigger, the installation input in 1 of which is connected to the output of the seventh SHIII element, the first and second inputs of which are connected respectively to the outputs of the first and third comparison elements, the first input of the last of which is combined with the first inputs of the first and second comparison elements, the input of the first delay element and the first input of the subtraction unit, the second input of the third comparison element is combined with the first inputs of the fourth and fifth comparison elements and connected to the first output of a constant voltage source, the second The output of which is connected to the second input of the first comparison element, the third output is connected to the first input of the sixth comparison element, the fourth output is connected to the first inputs of the second and third keys, the second input of the second terminal is connected to the output of the sixth element And, the output of the second key is connected to the subtractive the input of the first analog adder, the summed input of which is connected to the output of the fourth key, and the setup input to the zero state is connected to the output of the third OR element, the output of the first analog adder n with the second input of the fourth comparison element and the first input of the eighth OR element, the second input of which is combined with the second input of the fifth comparison element and connected to the output of the second analog adder, the output of the eighth OR element is connected to the second input of the sixth comparison element, the output of which is connected to the first the inputs of the seventh and eighth elements And, the second input of the seventh element And combined with the first inputs of the ninth and tenth elements And, and is connected to the output of the second delay element, the second input of the ninth element a AND is combined with the first input of the ninth OR element and connected to the output of the fourth comparison element, the second input of the tenth AND element is combined with the second input of the ninth OR element and connected to the output of the fifth comparison element, the output of the seventh AND element is connected to the first information the input of the shift register, the output of the ninth element And is connected to the second information input of the shift register and the subtractive input of the adder, The throttling input of which is combined with the third information input of the shift register is connected to the output of the tenth And element, the shift input of the shift register is combined with the counting input of the second frequency divider and connected to the output of the eleventh And element, which is the first output bus, the outputs of the shift register and the adders are the second and third output buses, respectively, the output of the second frequency divider is connected to the first input of the twelfth element AND, the second input of which is connected to the output of the ninth element OR, and the output is connected to the first input of the tenth OR element, the second input of which is combined with the second input of the fifth OR element, the first input of the sixth OR element and is connected to the output of the first frequency divider, the third input of the tenth OR element is combined with the second input of the sixth OR element, input set to 1 of the first trigger and is connected to the output of the thirteenth element AND, the output of the tenth element OR is connected to the inputs of the second and third delay elements, the output of the last of which is connected to the first inputs of the sixteenth and sixth About AND elements, the second input of the latter. Of which is connected to the direct output of the third trigger, the installation input in 1 of which is combined with the first input of the fourth key, the second input of the fourth OR element, the third input of the second OR element, and the second the input of which is combined with the input of the second element NOT and is connected to the second output in the mountain reference element, the output of the second element is NOT connected to the second input of the second element I, the third input of which is connected to the output of the first element NO, the second input of the second comparison element is combined with the second input of the subtraction unit and connected to the output of the first delay element, the output of the subtraction unit is connected to the inputs of the first and second valve elements, the output of the first valve element through an inverter is connected to the first input of the eleventh element OR, the third input of which is connected to the output of the second ventilation element, and the output is connected with the second inputs of the first and fourth keys, the output of the first element And is connected to the first inputs of the fifteenth and thirteenth elements And, the second input of the thirteenth element And connected to the direct output of the first trigger, the inverted output of which is connected to the second input of the fifteenth element I, the output of which is connected to the counting input of the first frequency divider, the second input of the eighth element And, and the first input of the eleventh element And, the second input of which is combined with the third input of the eighth element And and is connected to the output the twelfth element OR, whose inputs are connected to the corresponding outputs of the pulse counter, the counting input of which is connected to the output of the eighth element AND, and the installation input to O - to the output of the fifth OR element, the output of the first key is connected to the summing input of the second analog adder which is connected to the exit of the third a key, the second input of which is connected to the output of the fourteenth element I, the second input of which is connected to the direct output of the fourth trigger, the installation input to O of which is connected to the output of the second element of the IPI, t, -t 5 & / x (7 I no no Exit iii)  V3t: 2 V5r V6ry, too 001 GDI 001 101 one lao 0 (puf. 2