SU1691963A1 - Digital-to-analog converter - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in digital-to-analog data conversion systems, in particular, voltage setting units in devices controlling parameters of electronic products. The purpose of the invention is to simplify the device while maintaining the accuracy of the conversion. The D / A converter contains a register 1, a generator of 2 pulses, a source of 3 reference voltage, n converters 4.1-4. A code-time interval, an adder 5, a low-pass filter 6, n-1 RS-flip-flops 7.1-7. (N-1 ), block 8 elements I. n-1 elements AND 9.1-9. (n-1). A specific implementation of the code-time interval converter 4 is presented. A positive effect was achieved due to the introduction of n-1 RS-flip-flops, as well as additional connections between the units of the device. 1 hp f-ly, 3 silt

Description

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fi & 1

The invention relates to automation and computing lexnviiu and can be used in systems for converting digital information from analogue, in particular, to the installation voltage of devices 5 wah koigool paramefov radioelectronic products

The purpose of the isobrogeny is to simplify the device while maintaining the accuracy of the conversion .10

From FIG. Functional, diagrams of a digital converter are presented; . - The functional scheme is: - ,.: 3m: lg1; OL-interval interval; on fkg. ° - h,} М ЗН1-ё diagrams, referring to the 15th .v sh. Fpgmnnaluyu transform / 1 3.

Digital-to-W Ogo (converter (D / A) (f / l, 1) s, register 1, generator 2 pulses, 3 reference voltages, 20, p, p-outrs 4.1-4. Code-time f / terminal block. Adder 5 , lowpass filter 6, ni RS-flip-flops 7 .. (n-1), block 8 elements I, p-1 elements I 9.1-9. (n-1) .25

The converter is a code-time interval (Fig. 2) made in the form of a pulse counter 10, an object OR 11, an RS flip-flop 12 and a digital comparator 13.

CMPF:) th converter 30 (fi. I) as follows.

Nz to forms 1on: the inputs of register 1 are preceded by a smart code N. The number of bits is JOD TI, heating, where n is the number of downloaded: 1 conversion; K - number of 35 paspwa n each channel. Prior to the conversion of the input bus, the Start-up of the high level BVG g r. At the same time, block 8 sicMCH Ob Vj is blocked by the input of the system 1CH S |, at the first outputs of the press 40 raeov: h: 4 -1 -4. And the code-time signal is usgg.iovps 1 inoppen 1, on the outputs of HS -triggeoop - / ri-1) - level O and lie- memchy i 9 1-Part (n-1) ZEblokirooans according to the first in; Odock 45

The moment of the pseudokhod of the signal Start from high i i j8i i pa low is the beginning of the conversion process. By this transition n & ikayag tzpolnyatsya counter 10 pulses nepnofj converter 4.1 50 1SD-8pe1che1-. pchegwa / t pulse generation & 2, nenvir / 4 motors is equal to T0. At the front, the inputs bMCi-pGbOio of the comparator 13 with SUKHODs, with the output of the register 1 output group, receives the number 1 (the leading bits of the 55 M input code). L spp-i, the time interval Mi TO on anybody, CL ecg. A 10 pulses are formed by Ktv, argil N 1 as a result of the output of u / nt)} OHuro comparator

Level 1 is set. RS triggers 7.1 and 12 of the first converter J.1 of the time-interval are set to one (Fig. 3g, a) and a pulse with a duration proportional to N. is generated at the first output of the converter 4.1 code-interval. Signal 1 from the output of the trigger 7.1, the element 9.1 opens and the pulse formation begins at the output of the second code-time interval 7.2 converter. With the appearance of signal 1 at the output. The RS flip-flop 7.2 starts forming a pulse at the output of the next channel of the pre-base code in the time interval, etc. (FIG. 36, c, d).

When a 2k-ro pulse arrives at the input of the counter 10 of the converter 4.1 code-time interval by the overflow signal of the counter 10, the trigger 12 is set to the zero state and the next pulse of the pulse sequence begins to form at the first output of the converter 4.1, the code-time interval. These pulses turn on the corresponding element of block 8 of elements I. An adder 5, which can be implemented as an n-bit code-controlled divider with identical weights in all bits, forms at its output a pulse sequence with an amplitude equal to the voltage U0 of the source 3 of the reference voltage, pulse duration, proportional to the value of the N4 code, and the pulse duration

  R0. This pulse sequence is averaged by a low-pass filter 6, at the output of which a DC signal is generated, the level of which is proportional to the value of the higher bits of the input transform code, taking into account their weights.

The capacitance of the counters 10 of the pulses of the second channel is selected 2K times greater than the number of counters of the first channel. At the same time, the pulse following period at the output of the converter 4.2 is the code-time interval of the second conversion channel. For the 1st channel conversion, the pulse period T | Tm 2k G0-2 k,

Then the output voltage of the low pass filter b

Ub

- D1 I V G - A I G ° V

, 2

where a is the proportionality coefficient. Let, for example,,, and 1000 1000. Substituting these values into the above expression, we get

,)

The resulting expression, with an accuracy of the proportionality coefficient, coincides with the output signal for a conventional binary parallel conversion DAC.

This DAC is simpler than the prototype device, and its accuracy parameters are determined by the accuracy of the implementation of the adder 5 and the stability of the reference voltage of the source 3.

Claims (2)

1. A digital-to-analog converter containing a source of reference voltage, n-1 elements I, n converters code-time interval, the first outputs of which are connected to the corresponding first inputs of the block of elements I, the outputs of which are connected to the information inputs of the adder, the output of which is connected to the input of the filter low frequency, the synchronization input of the first converter, the code-time interval is combined with the synchronization input of the register and connected to the output of the pulse generator, the information inputs of the register are input A convertible code bus, characterized in that, in order to simplify while maintaining the conversion accuracy, p-1 RS-flip-flops are entered into it, the S inputs of which are connected to the second outputs of the corresponding converters to the OD-time interval, the information inputs of which are connected to the corresponding outputs of the corresponding register output group, the installation input of the first preconfiguration of the code-time interval is combined with the setting inputs of the remaining n 1 converters of the code-time interval, with the second input of the block of elements I. with the R-inputs n-1 RS-flip-flops and output bus Start, output i- ro RS-trigger is connected to the first input of the i-ro element And, where, 2 .., p-1, the second input of which connected to the output of the pulse generator, and the output connected to the synchronization input of the i + 1 converter of the code-time interval, the output of the low-pass filter is the output bus, the output of the source the reference voltage is connected to the auxiliary input of the adder. 2. The converter according to claim 1, characterized in that the code-time converter interval is made in the form of an RS trigger, an OR element, a pulse counter and a digital comparator, the first inputs of which are information inputs of the converter, the second inputs connected to the pulse counter outputs corresponding to the lower outputs, the overflow output of which is connected to the first input of the OR element, the output of which is connected to the R input of the RS flip-flop, 5 input which is connected to: the digital comparator output, the pulse counter synchronization input, the second input of the OR element, the digital comparator output, and the inverse output of the RS flip-flop are respectively input synchronization, the installation input, the second and the first outputs of the converter, the code-time interval. fig 2 fig.Z