SU1439599A1 - Device for monitoring pulse distributor - Google Patents

Abstract

The invention relates to automation and computing and can be used to control a pulse distributor during the main operation of control devices. The purpose of the invention is the extension of functionality due to the control of pulse distributors with changing e by the number of outputs. The goal is achieved by introducing an addition modulo two and a second delay element. 3 and

Description

with

x ate

with

The invention relates to automation for computing t-technics and can be used to control imgGuls distributors during the main operation of control devices.

The aim of the invention is to extend the functionality by controlling the distributors of I pulses with a variable number of outputs.

Figure 1 shows the functiondio-: on the diagram of the device distributor with; for the case of FIG. 2 and 3 - time diagrams of the operation of the proposed device i are presented for the control- and l distributor with the number of outputs ,,: equal to 5, 1. The device contains a controlled

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39599 .2

The module 1 confirms the zero state of the binary counter 6. The decoder 7 decrypts this state of the counter 6, and the output 14.1 of the decoder 7 has the cool signal. Therefore, the output of the AND element 8.1 will be a zero signal, since the zero signal is present at its first input .

At the outputs of the elements And 8.2-8.5 also a zero signal, as the zero signals from the outputs 12.2-12 "5 of the distributor 1 are present at their second inputs. Thus, at all inputs of the iUIl 9 element there is a zero signal, and consequently, at its output a zero signal, which will provide the output of the AND-NE element 10

ten

15

valve 1, delay element 2, 20 unit signal level, signal-delay element 3, element SHI 4, ensuring that there is no refusal, add-on 5. module two, counter 6, decoder 7, AND elements 8.1 - 8.5 groups, OR element 9, AND-NE element 10, clock input G1, outputs 12.1 - 12.5 of the controlled valve, output 13 of the device, outputs 14.1 - 14.5 decoder 7, output 15 of the element OR 9, output 16 of the element OR 4.

The delay element 2 is designed to prevent races, couplings with different delay times, signal s, 11 rk-1x-1x to the inputs of the elements AND 8.1 - 8.5. For this purpose, the error signal from the output of the 15th element IL 1 9 gates, with a delayed input pulse sequence. The time for the holder is chosen as 1/2 of the pulse duration with a jump of 2 or more or as.

limiter Further, when the post-TymieHHvi on the input of the binary counter 6 subsequent pulses, zero

25 will be successively displayed at the outputs of depfraurator 7, corresponding to the output of the distributor 1, at which at this moment there is a single signal. Thus, at the outputs of the AND 8.1–8.5 elements, a zero signal will be constantly present, which, having passed through the OR 9 element, will provide a unit level at the output of the AND – NE 10 element;

35

signal signaling the absence of distributor failures.

1/2 the duration of the interval between pulses with a well less than two

The delay element 3 is designed to compensate for the signal delay in the circuit of the control valve 1, - element 11PI A

The device works as follows.

When the power is turned on, the counter b is set to the zero state (installation circuits are not shown),

When the distributor is operating correctly (Fig. 2a), when 11 clock pulses are received at such an input, the common-mode signals are sent to the codes of the adding element 5 modulo two and, therefore, there will be a zero signal at its output. The first impuces from the run of 12.1 controlled g spread 45

50

If the distributor 1 fails, which causes one of its outputs, for example, output 12.3, to have no signal (FIG. 26), the signals in the inputs of the addition element 5 modulo two are disturbed. At the moment 12.3 of the controlled distributor 1, a single signal must appear at the first input of the adding element 5 modulo two, there will be a single signal, and a second signal at the second input, since at this moment there is no single signal at the output of the IPI 4 element. Thus, at the output of the modulo two element 5, there appears a single spgnal which through the element OR 9 enters the input of the element 10, at the output of which, coincident with the delayed input pulse sequence, a zero signal appears

unit level of the signaling signaling of the absence of failure

limiter Later, when TymieHHvi is injected into the binary counter 6 consecutive pulse input, the zero signal will successively appear at the outputs of the expander 7, corresponding to the output of the distributor 1, on which a single signal is present at that moment. Thus, at the outputs of elements AND 8.1-8.5, a zero signal will be constantly present, which, having passed through the element OR 9, will provide a unit level at the output of the element AND-NOT 10;

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35

signal signaling the absence of distributor failures.

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five

0

If the distributor 1 fails, which causes one of its outputs, for example, output 12.3, to have no signal (FIG. 26), the signals in the inputs of the addition element 5 modulo two are disturbed. At the moment 12.3 of the controlled distributor 1, a single signal must appear, at the first input of the adding element 5 modulo two there will be a single signal, and at the second input there will be a zero signal, since at this moment there is no single signal at the output of the IPI 4 element. Thus, at the output of the modulo two element 5, a single spgnal appears, which through the element OR 9 enters the input of the element 10, at the output of which, by coincidence with the delayed input sequence, of the pulses, zero signal appears.

t /

I testify to the ICG oG failure of the camcorder distributor 1.

In addition, the absence of pulses from the output 12.3 of the distributor 1 will cause the 5 signal to be distributed on the output of the pulse 12.4, and the zero signal is set on the output 14 of the decoder 7, 7 Therefore, on the output of the AND element, a single sigpap appears, as output 14.4 of the distributor 1 is present from the electronic signal, the signal from the output of the AND element 8.4, the element OR 9j enters the output of the AND-NOT 10 element and coincides with the delayed input sequence of pulses, the arrival of the element at the input of the element AND-NOT 10 appears zero signal sigpaliz irupgy about the failure of the controlled distributor 1. When the distributor 1 fails, resulting in two of its outputs, for example 12.2 and 12.3, simultaneously appear single pulses (Fig. 2c), a coincidence. signals at the inputs of the AND 8.2 element at the moment when single pulses are simultaneously present at the two outputs 12.2 and 12.3 of the distributor 1. Therefore, a single signal appears at the output of the AND 8.2 element that the torus OR 9 element at the second input of the element AND-NOT 10 and coincidentally with detained the input sequence of pulsesj arriving at the first input of the element AND-ЫЕ 10, forms at the output of the element I. others 10 a zero signal, indicating the failure of the distributor 1,

The failure of the distributor 1, characterized in that on one of its outputs J, for example, 12.2, a signal repeats twice, and on the other, for example, 12.3, there is no signal ("Over") that G4; I. on the phenomenon of Biopcro I; Pulse on code 12.2 of the distributor 1, the zero signal appears on code in the decoder 7, and at output 14.2 of the decoder 7 there is a left sigg. Consequently, at the outputs of the element And 8.2 there is a coincidence of 1 single sigcaps and at the output of the element And 8.2 there appears a single unit of chip; al, KOTOpbiii, passed through the second element of the IPI 9 to the second input of the element AND – IE AND) by coincidence with the delayed input sequence. received at the first input

3

Q 5 o 5 Q

five

five

0

five

WITH

99 of the I-11E 10 element, forms pa of the output of the element 1–10 of the zero with 1 signal, indicating the failure of the distributor 1,

When the sigils are frozen at one of the outputs of the distribution unit. 1, for example, pa output 12.4 (fig.Zb), xc; j, HT, desynchronization of signals, at the inputs of the adder 5 modulo two, since lia its first input will come 1g pulses per clock of the device through delay element 3, and the second input will be the unit potential from the output of an ShI element due to a single potential from the output 12.4 of the distributor 1. As a result, at the output of the adding element 5, according to slide two, there appears a single potential that through the IPI element 9 tgk wodnt to the input of the element II-IE 10. Except Moreover, the zero signal at 14.5 of the decoder 7 in this case, the nickname When it does not appear, since the potential measurement at the counting input of the counter b, when the signal at the output 12.5 of the distributor 1 appears, due to the constant potential at the output 12.4,

limiter 1. Consequently, when a pulse appears at the output 12.5 of the distributor 1, the state of counter 6 does not change, and therefore the next pulse will be the pulse from the output 12.1 of the distributor 1, which sets the counter 6 to the zero position. Therefore, the output 14.5 of the decoder 7 will be constantly the unit potential and a single pulse from the output 12.5 of the distributor 1 through the open element AND 8.5 passes the input element OR 9 and then to the second input of the element AND-NOT 10. The single signals coming from the output element 5 is added modulo DUYa n from the output of the element I 8.5. by coincidence with a delayed entrance of a sequence of pulses, npi-rxo-ing to the first NAND element

.10, formed zero signals at the output of the element, signaling the failure of the distributor 1.

Claims (1)

Invention Formula A device for controlling the distributor of pulses, containing two 1-SHI elements, a counter, a decoder, a group of elements AND, a first delay element and an NAND element, with inputs 5 devices for connecting the outputs 1 |: of the controlled distributor with rlepBoro on the 5th are connected to the first inputs of the AND elements of the group and to the inputs of the first OR element, the output of which is connected to the counting input of the counter, the outputs of which are connected to the input 1A39599 the delay element, the output of which is connected to the second input of the NAND element, characterized by the fact that, in order to expand the functionality due to the control of pulse distributors with a variable number of outputs, two descramblers are added to the device, the inverse outputs are co-Q and the second delay element, and foporo from the first to the fifth, the clock input of the device is connected to the Corresponding with the second inputs to the second input of the second delay element, jIentov And from the first to the nth group, the output of which is connected to the first the first input of which is connected with the first addition element modulo-two, the second-ith inputs of the second element Sh1I, the swarm input of which is connected to the output of which is connected to the first input of the first element TLI, the output element of the element AND-NOT, the output of which - modulo two is connected to the fct output of the device, the device’s clock input is the input (n + 1) -th input of the second OR element, the input of the device for connecting a device for connecting the clock 20 output of the controlled distribution of the controlled distribution valve to the reset input b and connected to the first input of the first About the counter. the delay element, the output of which is connected to the second input of the NAND element, characterized in that, in order to expand the functionality of the (n + 1) input, the input of the output devices of the connector About the counter. Phie.}