SU1429125A1 - Device for performing fourier transform - Google Patents

Description

(21) 4204257 / 24-24

(22) 02.02.87

(46) 10/07/88. Bul Number 37

(71) Institute of Electronics and Computer Engineering, Academy of Sciences of Latvian SSR

(72) I.I. Bilinsky, Ya.R., Viksna, I.B. Mednieks and R.F., Nemirovsky (53) 681.32 (088.8)

(56) USSR Copyright Certificate No. 571762, cl. G 0 | R 23/165, 1977.

. The author's svdedelstvo USSR 928363, cl. G 06 F 1/332, 1982.. (54) DEVICE FOR PERFORMING FURIER TRANSFORMATION

(57) The invention relates to automation and computing and can be used to determine the Fourier transform coefficients of real-time non-dipped signals. The purpose of the invention is to simplify the device. Delivered

The goal is achieved due to the fact that the device includes a generator

0-

1 pseudorandom sequence, analog-to-digital converter 2, switches 3,6,9,12, 11, blocks 4 and 5 of memory, address counters 7.8, generator 10 clock pulses, element OR 13, counter 14 cycles, block 15 constant memory, triggers 16, T7, the device includes two digital processing units, each of which contains elements EXCLUSIVE OR 18, accumulating adders 19, registers 20 and node 21 for solving linear equation systems. The device for performing the Fourier transform is based on the use of piecewise constant basis functions and their stochastic discretization simultaneously with the signal being processed. The use of piecewise constant functions R (t), taking the values +1, makes it possible to calculate the convolution without performing multiplication operations, 1 silt.

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This invention relates to automation.

B1..1 is a number of techniques and can be used to determine the coefficients of the Fourier transform of the continuous signals in real time,

; The purpose of the invention is to simplify the device.

The drawing shows a structural device for performing Fourier transform.

The device contains a pseudo-random pulse sequence generator, analog-to-digital converter 2, switch 3 blocks 4 and. 5) mi ti, switch 6, address accounts - 4biKH 7 and 8, switch 9, generator

clock impulse switches 11

12, item ШШ 13, counter 14, b | by 15 fixed memory, trigger-, 1 16 and 17,

In addition, the device also includes two identical n-channel block digital processing. Each block includes the elements EXCLUSIVE I.PI 18, accumulative adders 19 and registers 20, node 21 of the solution of the system of linear equations.

The device works as follows.

I The device for performing Fourier transform is based on the use of piecewise constant basis functions and their stochast 1-1 sampling simultaneously with the signal being processed. I Using piecewise constant functions R (t), taking values of ± .1, allows us to calculate the convolution without performing multiply multiply operations. The operation of multiplying the reference signal x (tn) by value, the function R {tj), is reduced to the assignment of the sign a and the convolution S. x {t) R (t,;,) to the operations of addition and subtraction.

In cases where the basis of the functions R (t) is orthogonal (Walsh, Haar and others functions), the convolution results are coefficients of the corresponding orthogonal signal transform. If it is necessary to have results in the basis of harmonic functions (the classical DFT), then it is useful to apply a non-orthogonal intermediate basis of piecewise-constant functions, and then perform a complicated recalculation of intermediate coefficients into Fourier coefficients,

Consider the use in the present invention of the functions Rc (t) and Bs (t) of the type of a meander (sign functions, respectively, signals cosZ iTft and .sin25rft).

Intermediate coefficients in. {And b {for the corresponding functions RcCt) HRs (t), (, 2.,., And / 2) in the discrete transformation are calculated by convolution formulas

N Z x (tORcL (t); .i (tj,

2 - x (tjR jj (1)

4t

five

0

0

50

where, 2 ,, .. N; N is the sample length of the signal samples. Each of the functions Rc (t) and Ri (t) can be decomposed into a Fourier series that contains components with odd frequencies. four

CSG () cosC2j-l) i4ff,

l) (2)

RM (t) sin (2j-i) iAf,

where uf l / NAtcp; (H)

Atcp is the average sampling interval. nation,

. f. Intermediate factors a and

B | and Fourier coefficients a -J. and b in accordance with (O and (2) links the system of linear equations

- (-1) - VT b 23GG

 one , .

bj,

(BUT)

ъ. - fr;

Having solved the system of equations (4), we arrive at the following final expressions for the Fourier coefficients of the transformed signal di.

(five)

five

0

five

 Г ((-1) а 4 i- () Г IT г I 1

i i L TjTT JH) g.

™ -. .

- the part of the expression in brackets is intact.

 From (5) it follows that all the Fourier coefficients with numbers are directly equal to the corresponding intermediate coefficients multiplied by the constant 7G / 4.

As is well known, stochastic discretization allows removing the restrictions imposed by Kotelnikov's theorem on the upper limit of the spectrum of the signal being converted, and processing without overlapping signals with frequencies greater than half the sampling frequency. theoretically unlimited spectrum, stochastic discretization of the processed signal and basis functions at coinciding moments of time is fundamentally necessary, edlagaemom device Q pseudorandom sequence of time intervals between the sampling instants t is given by the algorithm of the generator 1 pseudorandom pulse sequence (GPSIP) Since d specify the algorithm, it can be imple-g Call software. This allows the sequence to be calculated in advance.

Rcl () values of all functions of the intermediate basis for each 2 o of sampling time ty and write this sequence into block i 5 of memory. In the process of converting the input signal, the A / D converter 2 is clocked at times t with pulses that are 2V

Express the GPSIP 1. This achieves the effect of the stachastic discretization of the signal and the functions of the intermediate basis at coincident times. From ADC output.2, the samples i: (tn) 30 of the signal in the direct code through switch 3. arrive at the input of memory block 14 or at the input of memory block 5, depending on which of them is currently running record function. The operation mode of the device blocks is determined by the state of the trigger 17, which controls all the switches. If the output of the trigger 17 is a logical unit, then the memory block 4 operates in the write mode, and the memory block 5 operates in the read mode. Accordingly, the write counter 7 in the write mode operates which is clocked through the switch 9 of the same pseudo .g Before the light pulse sequence, as ADC 2. At this time, the address counter 8 operates in the mode of reading the information recorded in memory block 5 and is switched through gp switch 9 by the pulse sequence generated by the GTI 10. After recording in memory block 4 sequences from N count A signal appears at the output of the transfer of the address counter 7 gg, a pulse appears, which through the OR element 13 arrives at the counting input of the trigger 17, changing its output potential to a logical zero and:

35

Q d

about b

0

about g p g:

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and. thereby changing the control signal of the switches 3,6,951 and 12, whereby the memory unit 4 goes into the read mode of the recorded signal sample, and the memory unit 5 goes into the write mode of the next sample without a sampling start, which results in processing on the contiguous samples . The pulse sequence from the GTI 10 now goes through the switch 9 to the input of the address counter 7, and pseudo-randomly from the output of the GPSU 1 to the input of the address counter 8. Orgak; C, d, o -1 cycle counts x (t), xlt) 5,, .х. (Ii ,,) from the memory block successively arrive at the input of the switch 11, From the first output of the switch II, the sign bit of the reference xitc supplied to the combined second inputs of the e-mails EXCLUSIVE VJU l 18 of both digital processing units. . absolute reference x {uk. ) Remove: .c from the BTopoiTi of the output of the switch Pi is fed. on the union. second inputs and.; grappling adders 10 digital processing units, Odin.kh: re: -; with the addressing of the memory block 4 by the meter 7 through the switch 6 and the counter for 14 cycles it is the code of the address of the block 15 of the permanent memory and || it is provided to consider the functions R, (t ,,) and Rs (t |.) of an intermediate basis,

In Kakhsdom, Mr. I. and ickle from Permanent Memory Block 5, which has a 2n output o.

The values of f fs of the functions Rc nr + lJ (t) of the n functions (tv;), where ,, .. () is the decimal code of the number written in the binary account of the 14 number of the read cyclone; 1 1.2 ... p. Binary samples of functions Rcl tn) taken from the p outputs of the fixed memory unit 15, are fed to the first inputs of the corresponding elements EXCLUSIVE W1I 18 of the first digital processing unit, binary readings of the functions RsCti), supplied from the other n outputs of the fixed memory unit 15, are fed to the first inputs of the corresponding elements of the URIU or 18 of the second digital processing unit. The EXCLUSIVE OR 18 elements execute the operations of multiplying the characters, the signals from their outputs are fed to the sign inputs of the corresponding accumulating adders 19, specifying the operation code - addition or subtraction. In NaI .51429125

karivatyh adders 19 carried out - with the calculation of intermediate coefficients | eit in accordance with the expression (1), After the completion of the g-th cycle

nose floor

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; I1 values are rewritten into the corresponding registers 20, from the output of which are fed to the corresponding inputs of nodes 21. At node 21 of solving linear equation systems using formulas Q (), operations of P11 intermediate factors into Fourier coefficients are performed. From the output of the first node 21, the values the coefficients ai, from the output of the second — the K values of the Eudeueits 1. With this, the coefficients with the numbers i5.N / 6 in accordance with

(five)

are broadcast to the output by multiplying by the constant g / 4. A single device for performing a Fourier transform containing a pseudo-random sequence generator, the output of which is connected to the clock input of the analog-digital converter, whose information input is the information input of the device, a fixed memory unit, 1 15 e (, n; n / 2; N - conversion size) the outputs of the first and second groups of which are connected to the inputs of the groups of the first and second digital processing units respectively, whose outputs are the first and second information outputs of the device va, each of the digital processing unit comprises n EXCLUSIVE OR elements, accumulating n

20

c in l

temporarily with the completion of the g-th cycle, the signal from the transfer output of the address counter 7 through the switch 12 is input to the counter of 14 cycles, setting the address of the block 15 constant

memory for the (r + O th read cycle. 25 sum 1 1, p registers and the decision block In the (r + l) - M cycle again from block 4 of the memory of the linear equation system, 1st

using the same sequence of L cycles.

Claims (1)

Invention Formula A device for performing a Fourier transform containing a pseudo-random sequence generator, the output of which is connected to the clock input of the analog-digital converter, whose information input is the information input of the device, fixed memory block, 1e (, n; n4N / 2; N is size transformations) the outputs of the first and second groups of which are connected to the inputs of the groups of the first and second digital processing units, respectively, whose outputs are the first and second information outputs of the device, n When in use, each of the digital processing unit comprises n elements exclusive OR collecting n sum1 1atorov, n registers and node of the solution of the system of linear equations, 1st Ti reads the sequence of reports x (t), and from block 15 of the permanent memory the values of the functions () H- (A) and R & tnCt-t-l) are read. (tt). The procedure for calculating the next group of intermediate coefficients is as follows. the same as in the i-th cycle, K; at the end of the (r + l) -th cycle, previous results are written in res. 20, already recalculated and installed, and overwritten in registers 20 of the next group of intermediate coefficients After the completion of L read cycles, the signal from the transfer output of the counter 14 cycles arrives at the input to the zero setting of the trigger 16, which by its output signal prohibits further operation of the GTI 10 and completes the processing of the signal sample recorded in memory block 4. After completion of writing to memory block 5, the next sampling of the signal at the output of counter 8, the transfer signal is transmitted, which through the OR 13 element is fed to the counting input of the trigger 17, changing the operation mode of the memory blocks 4 and 5, and the setup input the trigger unit 16, enabling the GTI 10 and starting reading the signal sample recorded in memory block 5, the processing of this sample is done in the same order from the input of which is connected to the output of the 1st 0 B five - a register whose information input is connected to the output of the 1st accumulating adder, a clock input of which is connected to the output of the 1st zle, an EXCLUSIVE IL, element whose first input is the input of a group of a digital processing unit whose first input are interconnected second the inputs of the elements EXCLUSIVE OR, the information inputs of the accumulating adders of g; are interconnected and are the second Q input of a digital processing unit whose output is the output of a linear equation system solving node, characterized in that, in order to simplify the device, it contains two memory blocks, two triggers, five switches, an OR element , two address counters, cycle counter and clock generator, the output of which is connected to the first information input of the first switch, the first and second outputs of which are connected to the counting inputs of the first and second address counters, respectively whose output outputs are connected to the address inputs of the first and second memory blocks, respectively, and the first and second information inputs of the second switch, respectively, the output of which is connected to the first address input of the memory block, the second address input of which is connected to the information output of the cycle counter, the counting input of which is connected to the output of the third switch, the first and second information inputs of which are connected respectively to the first and second inputs of the OR element and the are connected to the transfer outputs of the first and second address counters, respectively; the output of the OR element is connected to the installation input of 1 of the first trigger and the clock input of the second trigger, the output of which is connected to the control inputs of the first second, third, fourth, and nth switches, the output of the analog-digital converter is connected to the information The first input of the fourth switch and the second outputs of which are connected to the information inputs of the first and second memory blocks, respectively, the outputs of which are connected respectively to the first and second information inputs of the fifth switch, the first and second outputs of which are connected respectively to the first and second inputs of the first and second digital processing units, the transfer output of the cycle counter is connected to the installation input in O of the first trigger, the output of which is connected to the stop input of the clock pulse generator pulses, and the output of the pseudo-random sequence generator is connected to the second information input of the first switch.