SU1418702A1 - Device for altering by unit an n-digit binary number - Google Patents

Abstract

The invention relates to computing and can be used in arithmetic units of high-speed computers. The purpose of the invention is to enhance the functionality by changing the binary number by a unit of arbitrary bit and detecting the overflow of the bit grid and a negative result. The device contains n elements OR NONE 1, n elements OR 2, two groups of n elements EXCLUSIVE OR 3, 5 and element NON 6. An n-bit binary number is fed to the first information input of the device, and a n-bit number to the second information input a control code containing a single unit in the category in which it is summed or subtracted. The first one-bit control input receives a signal, allowing the source code to change, and the second, the sign of this change. On the n-bit output of the device, the code of the output number changed by the unit of the bit, which is determined by the control code, or the code of the original number without change is formed. The one-bit output of the device receives a signal when there is an overflow of the discharge grid when podmming or a negative result when subtracting. 1 il. and

Description

Yu

12

The invention relates to computing and can be used in arithmetic units of fast-computing computers. The purpose of the invention is to expand the functionality by changing the binary number by the unit of the spontaneous bit and detecting the overflow of the bit grid and the negative result.

 The drawing shows the scheme of the proposed device.

I The device for changing the n-bit of the d-th binary number by one contains n elements OR-NOT 1, n elements OR 2, the first group of n elements iieHTOB. EXCLUSIVE OR 3, n elements AND 4, the second group of n elements represents the number of the bit of code B containing the lowest (to the right) lowest unit. In particular, to add or subtract from an arbitrary nth digit of the number a, it is convenient to choose as the code B the code with the components, b (w) 1, b (1) O, V; t t, i.e. code containing a single unit in

Pc-raz de. R

If the result is LO, 2 | those. in the case of overflow of the discharge grid or a negative result, the output 12 of the device saves 5 s and the potential of a logical unit () indicates the incorrectness of the result.

r P ht-tr

If the result is C6 0, 2, then at the second output 12, an EXCLUSIVE OR 5 is set, the element is NOT 6, 20 logical zero (), specified 25

J5

the first 7 and second 8 n-bit information inputs, the first 9 and second 10 one-bit control inputs, the r-p n-bit output 11, and the second one-bit output 12.: The device operates as follows.

I In the initial state at a potential of logical zero, the inputs 7-10 of the device at its first output 11 30 also set the potential of a logical zero, and at the second output 12 - the potential of a logical unit (W 1), indicating the absence of a result at the first output 11.

Upon admission to the first information input of 7 p-bit binary code A {a (p), a (p-1), ..., a (1) j

p P a positive number and a a (i) 2,

where n6 {l, 2, ..., pe Z {..., - 1, O,,, ...), in particular, for p -1, a is a natural number, and for p - (n + 1) and 2G 1 is a number. Presented in the form of a fixed comma, and to the second information input 8 n-bit binary non-zero code B b (n), b (n-1), ..., b (1) j depending on the values of the potentials S and V on the first 9 and second 1, control inputs and on the first output 11 of the device, the following result C is formed:

 and at S 1, Ve {0, (1)

C: C:

r4P1

a + b (m) 2 at 8 0, Y 0;

p4-t

with S O, V 1;

(2) (3)

WITH; a-b (m) -2 where m: min {ieQ, 2, ..., nyb (i) 1 (4)

for a correct result.

In the case of (1), when a signal arrives at the first control input 9 of the device, regardless of the signal V {(O, 1) j., The second control input 10 at the output of the group of elements OR NOT 1 produces the zero code ZZ ( n), Z (n-1), ..., Z (1), where Z (i) O Vl e, 2, ..., nj, arriving at the third inputs of the EXCLUSIVE OR 3 elements, and NOT at the output of the elements 6 — a zero potential is established, which, by blocking the elements AND 4, forms the zero code VV (n), V (n-1), ..., V (1) at the second inputs of the elements EXCLUSIVE OR 3. Therefore the code A coming from the first information entry device 7 on

40, the first inputs of the EXCLUSIVE., OR 3 elements, without change, pass to the output 11 of the device. In this case, the output 12 of the device due to the blocking of the nth element And 4 is set to zero

d5 potential (), corresponding to the correct result.

In the case of (2), a signal is received at the first control input 9 of the device. The code B submitted to the second information input B of the device is converted into a group of elements OR NOT to the code Z {z (n), Z (n-1), ..., Z (1), where

Z (i), V b (j) V8Vie G1,2, ..., p, otku- j-i - J

55 yes it follows that Z (i), 2

m-1), Z (i) OViefm, m + 1, ..., n, where the number m, defined by relation (4), is the bit number of the code B containing the low unit.

is the bit number of the B code containing the last (to the right) lowest unit. In particular, to add or subtract from an arbitrary nth digit of the number a, it is convenient to choose as the code B the code with the components, b (w) 1, b (1) O, V; t t, i.e. code containing a single unit in

t-raz de. R

If the result is LO, 2 | those. in the case of overflow of the discharge grid or a negative result, the one at output 12 of the device saves 5–5 s the potential of a logical unit (), indicating the incorrectness of the result.

r P ht-tr

If the result is C6 0, 2, then the second output 12 is set to 5

five

0

for a correct result.

In the case of (1), when a signal arrives at the first control input 9 of the device, regardless of the signal V {(O, 1) j., The second control input 10 at the output of the group of elements OR NOT 1 produces the zero code ZZ ( n), Z (n-1), ..., Z (1), where Z (i) O Vl e, 2, ..., nj, arriving at the third inputs of the EXCLUSIVE OR 3 elements, and NOT at the output of the elements 6 — a zero potential is established, which, by blocking the elements AND 4, forms the zero code VV (n), V (n-1), ..., V (1) at the second inputs of the elements EXCLUSIVE OR 3. Therefore the code A coming from the first information entry device 7 on

0, the first inputs of the EXCLUSIVE., OR 3 elements, without change, pass to the output 11 of the device. In this case, the output 12 of the device due to the blocking of the nth element And 4 is set to zero

5 potential (), corresponding to the correct result.

In the case of (2), a signal is received at the first control input 9 of the device. The code B submitted to the second information input B of the device is converted by a group of elements OR NOT to the code Z {z (n), Z (n-1), ..., Z (1), where

Z (i), V b (j) V8Vie G1,2, ..., p, otku- j-i - J

5 yes it follows that Z (i), 2

m-1), Z (i) OViefm, m + 1, ..., n, where the number m, defined by relation (4), is the bit number of the code B containing the low unit.

3141

If the second control input 10 has a signal V O, the code A of the first information input 7 progresses without changing the second group of elements EXCLUSIVE E or 5 to the second inputs of the elements OR 2. Due to the input to the first inputs of the elements OR 2 Z codes at their outputs code is generated

and u (i) / U (i) Z (i) Va (i) Vie {l, 2,

..., n. (5)

where U (i) 1 V ie l, 2, ..., m-l, U (i) a (i) V, m + 1, ..., n1.

The passage through the elements AND 4, n-1 of the low-order bits of the U code is converted into n-1 most significant bits of the V code, the low-order bits of which are determined by signal S 1 from the output of the HE element 6. The V (n), V (n- 1), ..., V (1), where

C (i) a (i) ® V (i) ez (i)

0

702

V (1) S 1, V (i) au (j) & SVie {2, 3, ..., nl, arriving at the second inputs; elements are EXCLUSIVE OR 3, contains ones in K younger bits and zeros in (p-K) older bits, where

К:, m + 1, ..., n} / U (i) a (i)

  m (6)

is the number of the low-order zero of the U code. The code Z, which arrives at the third inputs of the EXCLUSIVE OR 3 elements, contains units in m-1, lower-order bits and zeros in n-1 + 1 high-order bits. Consequently, the code A coming from the first information input 7 of the device to the first inputs of the EXCLUSIVE OR 3 elements is converted by them into a code with fc (n), C (n-1), ..., C (1) j and is assigned to the first output 11 devices, and for this code

five

“A (i) iefl, 2m-l;

a (i), m + l, ..., a (i), k + 2n;

(7)

On the other hand, by virtue of the transfer rule in the summation of binary numbers, exactly the same expressions characterize bits C (i) of the binary number C defined by relation (2), i.e. code C is the desired one.

Simultaneously with the formation of the code V, the nth element of AND 4 interrupts output 12 of the device.

. W a u (i)) & S,

corresponding to a logical zero if the indicated number K exists, and to a logical unit, if such a number does not exist, i.e. There is an overflow of the result grid of result 45

In case (3), when the first control input 9 of the device receives a signal, and the second control input 10 has a signal V 1, code A is inverted by the second group of IC-gQ elements KEY OR 5, as a result of which the outputs of the OR elements 2 are generated code.

and fu (i) / U (i) Z (i) Va (i), 2,

..., nl, (9)

where U (i) 1 V, 2, ..., m-l, U (i) a (i) V i-e (m, n + 1 ,, .., n.

thirty

35

40

- 45

gQ

55

Code V, which arrives at the second inputs of the EXCLUSIVE OR 3 elements, as well as in case (2), contains units in K lower-order bits and zeros (n-K) higher-order bits, where

K: m + 1, ..., UJ / U (i)

 i (i) (10)

i

is a minor number

zero code and, defined by expression (9). The difference between relations (10) and (6) is to replace the values of a (i) with inverted a (i): 1-a (i). At output 11 of the device, a code C is formed, characterized by relations (7) and differing from the similar code in case (2) only by the fact that the number K is given by the relation (10) ,. and not (7). In accordance with the transfer rules for subtracting binary numbers, relation (7), subject to condition (10), defines the bits C (i) of the binary number C, which is calculated by formula (3). The signal W in accordance with (8) at the output 12 of the device in this case assumes a zero value at ab 0 and a single value at a-g-0.

To increase the regularity of the "homogeneity of the structure of the device when it is implemented as an integral

schemes it is advisable (based on de Morgan’s law) to replace each element AND 4 and each element OR 2 with an element OR NOT with the same number of inputs

Claims (1)

Invention Formula A device for changing an n-bit binary number by one,; containing the first group of n elements EXCLUSIVE OR, n-1 elements AND, the second group of n-1 elements EXCLUSIVE OR, and the first input of the i-ro element EXCLUSIVE OR of the second group (Vie {l, 2, ..., n-II) is connected to the i-th bit of the first information input of the device; the input of each element of the EXCLUSIVE-1CEE OR of the second group is connected to the | second control input of the device | va, the output of the i-ro element AND is connected | to the second input of the (i + 1) -th element EXCLUSIVE OR of the first group, the first input d j-ro of the EXCLUSIVE OR element of the first group (VJ cfl, 2, ..., n) soy is dinene with JM bit of the first shape of the 1st INPUT of the device, and its output is with JM bit of the output of the result of the device that distinguishes € so that, for the purpose of expansion; functionality by changing the binary number by one five 0 five 5 th 0 arbitrary discharge and detection of an overflow of the discharge grid and a negative result, n elements are entered, the elements are NOT, n are the elements OR the element is NOT, the nth element is AND and the nth element is EXCLUSIVE OR of the second group, and the input of the element is NOT connected to the first control the input of the device and the first input of each element W1N-NOT, the output of the element is NOT connected to the second input of the first element EXCLUSIVE OR of the first group and the first input of each element AND, Oc + 1) -th input of the j-ro element OR-NOT (Vkefl, 2, ..., jj) is connected to the kM bit of the second information input of the mouth The output, j-ro output of the WL-NOT element is connected to the third input of the j-ro element EXCLUSIVE OR of the first group and the second input of the j-ro element OR, the first input of which is connected to the output of the j-ro element EXCLUSIVE OR of the second group, and the output is from (j + 1) -M input of the Hth element AND (Vm6 | j, j + 1, ..., n1), the output of the nth element AND is the device indication output, and the first and second inputs of the nth element EXCLUSIVE OR of the second group are connected respectively to the n-th bit of the first information input of the device and the second control input of the device.